i386: Allow only registers with VALID_INT_MODE_P modes in movstrict<mode> [PR93997]

*movstrict<mode>_1 insn pattern allows only general registers,
so we have to reject modes not suitable for general regs in
corresponding movstrict<mode> expander.

	PR target/93997
	* config/i386/i386.md (movstrict<mode>): Allow only
	registers with VALID_INT_MODE_P modes.

testsuite/ChangeLog:

	PR target/93997
	* gcc.target/i386/pr93997.c: New test.

gcc/ChangeLog

+2020-03-02  Uroš Bizjak  <ubizjak@gmail.com>
+
+	PR target/93997
+	* config/i386/i386.md (movstrict<mode>): Allow only
+	registers with VALID_INT_MODE_P modes.
+
 2020-03-02  Andrew Stubbs  <ams@codesourcery.com>
 
 	* config/gcn/gcn-valu.md (dpp_move<mode>): New.

gcc/config/i386/i386.md

@@ -2778,7 +2778,7 @@
 {
   gcc_assert (SUBREG_P (operands[0]));
   if ((TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
-      || GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT)
+      || !VALID_INT_MODE_P (GET_MODE (SUBREG_REG (operands[0]))))
     FAIL;
 })
 

gcc/testsuite/ChangeLog

+2020-03-02  Uroš Bizjak  <ubizjak@gmail.com>
+
+	PR target/93997
+	* gcc.target/i386/pr93997.c: New test.
+
 2020-03-02  Martin Sebor  <msebor@redhat.com>
 
 	PR tree-optimization/92982

gcc/testsuite/gcc.target/i386/pr93997.c

+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-march=athlon-4" } */
+
+#include "../../c-c++-common/vector-scalar.c"