Commit b5ccb9ed by Eric Botcazou Committed by Eric Botcazou

re PR bootstrap/58509 (ICE in calc_dfs_tree, at dominance.c:397 during Ada runtime build)

	PR bootstrap/58509
	* config/sparc/sparc-protos.h (widen_mem_for_ldd_peep): Declare.
	(registers_ok_for_ldd_peep): Move around.
	* config/sparc/sparc.c (widen_mem_for_ldd_peep): New.
	* config/sparc/sparc.md (widening peepholes): Use it.

From-SVN: r203518
parent fd7e5084
2013-10-14 Eric Botcazou <ebotcazou@adacore.com>
PR bootstrap/58509
* config/sparc/sparc-protos.h (widen_mem_for_ldd_peep): Declare.
(registers_ok_for_ldd_peep): Move around.
* config/sparc/sparc.c (widen_mem_for_ldd_peep): New.
* config/sparc/sparc.md (widening peepholes): Use it.
2013-10-14 Richard Biener <rguenther@suse.de> 2013-10-14 Richard Biener <rguenther@suse.de>
PR middle-end/58712 PR middle-end/58712
......
...@@ -81,7 +81,9 @@ extern const char *output_probe_stack_range (rtx, rtx); ...@@ -81,7 +81,9 @@ extern const char *output_probe_stack_range (rtx, rtx);
extern const char *output_cbcond (rtx, rtx, rtx); extern const char *output_cbcond (rtx, rtx, rtx);
extern bool emit_scc_insn (rtx []); extern bool emit_scc_insn (rtx []);
extern void emit_conditional_branch_insn (rtx []); extern void emit_conditional_branch_insn (rtx []);
extern int registers_ok_for_ldd_peep (rtx, rtx);
extern int mems_ok_for_ldd_peep (rtx, rtx, rtx); extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);
extern rtx widen_mem_for_ldd_peep (rtx, rtx, enum machine_mode);
extern int empty_delay_slot (rtx); extern int empty_delay_slot (rtx);
extern int emit_cbcond_nop (rtx); extern int emit_cbcond_nop (rtx);
extern int eligible_for_return_delay (rtx); extern int eligible_for_return_delay (rtx);
...@@ -95,7 +97,6 @@ extern int mem_min_alignment (rtx, int); ...@@ -95,7 +97,6 @@ extern int mem_min_alignment (rtx, int);
extern int pic_address_needs_scratch (rtx); extern int pic_address_needs_scratch (rtx);
extern int register_ok_for_ldd (rtx); extern int register_ok_for_ldd (rtx);
extern int memory_ok_for_ldd (rtx); extern int memory_ok_for_ldd (rtx);
extern int registers_ok_for_ldd_peep (rtx, rtx);
extern int v9_regcmp_p (enum rtx_code); extern int v9_regcmp_p (enum rtx_code);
/* Function used for V8+ code generation. Returns 1 if the high /* Function used for V8+ code generation. Returns 1 if the high
32 bits of REG are 0 before INSN. */ 32 bits of REG are 0 before INSN. */
......
...@@ -8543,6 +8543,16 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) ...@@ -8543,6 +8543,16 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
return 1; return 1;
} }
/* Return the widened memory access made of MEM1 and MEM2 in MODE. */
rtx
widen_mem_for_ldd_peep (rtx mem1, rtx mem2, enum machine_mode mode)
{
rtx x = widen_memory_access (mem1, mode, 0);
MEM_NOTRAP_P (x) = MEM_NOTRAP_P (mem1) && MEM_NOTRAP_P (mem2);
return x;
}
/* Return 1 if reg is a pseudo, or is the first register in /* Return 1 if reg is a pseudo, or is the first register in
a hard register pair. This makes it suitable for use in a hard register pair. This makes it suitable for use in
ldd and std insns. */ ldd and std insns. */
......
...@@ -6971,9 +6971,10 @@ ...@@ -6971,9 +6971,10 @@
(const_int 0))] (const_int 0))]
"TARGET_V9 "TARGET_V9
&& mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)" && mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)"
[(set (match_dup 0) [(set (match_dup 0) (const_int 0))]
(const_int 0))] {
"operands[0] = widen_memory_access (operands[0], DImode, 0);") operands[0] = widen_mem_for_ldd_peep (operands[0], operands[1], DImode);
})
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "memory_operand" "") [(set (match_operand:SI 0 "memory_operand" "")
...@@ -6982,9 +6983,10 @@ ...@@ -6982,9 +6983,10 @@
(const_int 0))] (const_int 0))]
"TARGET_V9 "TARGET_V9
&& mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)" && mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)"
[(set (match_dup 1) [(set (match_dup 1) (const_int 0))]
(const_int 0))] {
"operands[1] = widen_memory_access (operands[1], DImode, 0);") operands[1] = widen_mem_for_ldd_peep (operands[1], operands[0], DImode);
})
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -6993,10 +6995,11 @@ ...@@ -6993,10 +6995,11 @@
(match_operand:SI 3 "memory_operand" ""))] (match_operand:SI 3 "memory_operand" ""))]
"registers_ok_for_ldd_peep (operands[0], operands[2]) "registers_ok_for_ldd_peep (operands[0], operands[2])
&& mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])" && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
[(set (match_dup 0) [(set (match_dup 0) (match_dup 1))]
(match_dup 1))] {
"operands[1] = widen_memory_access (operands[1], DImode, 0); operands[1] = widen_mem_for_ldd_peep (operands[1], operands[3], DImode);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));") operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
})
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "memory_operand" "") [(set (match_operand:SI 0 "memory_operand" "")
...@@ -7005,10 +7008,11 @@ ...@@ -7005,10 +7008,11 @@
(match_operand:SI 3 "register_operand" ""))] (match_operand:SI 3 "register_operand" ""))]
"registers_ok_for_ldd_peep (operands[1], operands[3]) "registers_ok_for_ldd_peep (operands[1], operands[3])
&& mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)" && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
[(set (match_dup 0) [(set (match_dup 0) (match_dup 1))]
(match_dup 1))] {
"operands[0] = widen_memory_access (operands[0], DImode, 0); operands[0] = widen_mem_for_ldd_peep (operands[0], operands[2], DImode);
operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));") operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
})
(define_peephole2 (define_peephole2
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
...@@ -7017,10 +7021,11 @@ ...@@ -7017,10 +7021,11 @@
(match_operand:SF 3 "memory_operand" ""))] (match_operand:SF 3 "memory_operand" ""))]
"registers_ok_for_ldd_peep (operands[0], operands[2]) "registers_ok_for_ldd_peep (operands[0], operands[2])
&& mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])" && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
[(set (match_dup 0) [(set (match_dup 0) (match_dup 1))]
(match_dup 1))] {
"operands[1] = widen_memory_access (operands[1], DFmode, 0); operands[1] = widen_mem_for_ldd_peep (operands[1], operands[3], DFmode);
operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));") operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));
})
(define_peephole2 (define_peephole2
[(set (match_operand:SF 0 "memory_operand" "") [(set (match_operand:SF 0 "memory_operand" "")
...@@ -7029,10 +7034,11 @@ ...@@ -7029,10 +7034,11 @@
(match_operand:SF 3 "register_operand" ""))] (match_operand:SF 3 "register_operand" ""))]
"registers_ok_for_ldd_peep (operands[1], operands[3]) "registers_ok_for_ldd_peep (operands[1], operands[3])
&& mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)" && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
[(set (match_dup 0) [(set (match_dup 0) (match_dup 1))]
(match_dup 1))] {
"operands[0] = widen_memory_access (operands[0], DFmode, 0); operands[0] = widen_mem_for_ldd_peep (operands[0], operands[2], DFmode);
operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));") operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));
})
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -7041,10 +7047,11 @@ ...@@ -7041,10 +7047,11 @@
(match_operand:SI 3 "memory_operand" ""))] (match_operand:SI 3 "memory_operand" ""))]
"registers_ok_for_ldd_peep (operands[2], operands[0]) "registers_ok_for_ldd_peep (operands[2], operands[0])
&& mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])" && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
[(set (match_dup 2) [(set (match_dup 2) (match_dup 3))]
(match_dup 3))] {
"operands[3] = widen_memory_access (operands[3], DImode, 0); operands[3] = widen_mem_for_ldd_peep (operands[3], operands[1], DImode);
operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));") operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));
})
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "memory_operand" "") [(set (match_operand:SI 0 "memory_operand" "")
...@@ -7053,11 +7060,11 @@ ...@@ -7053,11 +7060,11 @@
(match_operand:SI 3 "register_operand" ""))] (match_operand:SI 3 "register_operand" ""))]
"registers_ok_for_ldd_peep (operands[3], operands[1]) "registers_ok_for_ldd_peep (operands[3], operands[1])
&& mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)" && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
[(set (match_dup 2) [(set (match_dup 2) (match_dup 3))]
(match_dup 3))] {
"operands[2] = widen_memory_access (operands[2], DImode, 0); operands[2] = widen_mem_for_ldd_peep (operands[2], operands[0], DImode);
operands[3] = gen_rtx_REG (DImode, REGNO (operands[3])); operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
") })
(define_peephole2 (define_peephole2
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
...@@ -7066,10 +7073,11 @@ ...@@ -7066,10 +7073,11 @@
(match_operand:SF 3 "memory_operand" ""))] (match_operand:SF 3 "memory_operand" ""))]
"registers_ok_for_ldd_peep (operands[2], operands[0]) "registers_ok_for_ldd_peep (operands[2], operands[0])
&& mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])" && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
[(set (match_dup 2) [(set (match_dup 2) (match_dup 3))]
(match_dup 3))] {
"operands[3] = widen_memory_access (operands[3], DFmode, 0); operands[3] = widen_mem_for_ldd_peep (operands[3], operands[1], DFmode);
operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));") operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));
})
(define_peephole2 (define_peephole2
[(set (match_operand:SF 0 "memory_operand" "") [(set (match_operand:SF 0 "memory_operand" "")
...@@ -7078,10 +7086,11 @@ ...@@ -7078,10 +7086,11 @@
(match_operand:SF 3 "register_operand" ""))] (match_operand:SF 3 "register_operand" ""))]
"registers_ok_for_ldd_peep (operands[3], operands[1]) "registers_ok_for_ldd_peep (operands[3], operands[1])
&& mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)" && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
[(set (match_dup 2) [(set (match_dup 2) (match_dup 3))]
(match_dup 3))] {
"operands[2] = widen_memory_access (operands[2], DFmode, 0); operands[2] = widen_mem_for_ldd_peep (operands[2], operands[0], DFmode);
operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));") operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));
})
;; Optimize the case of following a reg-reg move with a test ;; Optimize the case of following a reg-reg move with a test
;; of reg just moved. Don't allow floating point regs for operand 0 or 1. ;; of reg just moved. Don't allow floating point regs for operand 0 or 1.
......
2013-10-14 Eric Botcazou <ebotcazou@adacore.com>
* gnat.dg/specs/opt1.ads: New test.
2013-10-14 Richard Biener <rguenther@suse.de> 2013-10-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/58640 PR tree-optimization/58640
......
-- { dg-do compile }
-- { dg-options "-O2" }
with Ada.Strings.Unbounded; use Ada.Strings.Unbounded;
package Opt1 is
type Ptr is access all Integer;
type R1 is record
I1 : Integer;
I2 : Integer := 0;
I3 : Integer;
end record;
type R2 is record
P : Ptr;
F1 : R1;
end record;
type R3 is record
S : Unbounded_String;
F1 : R2;
I : Integer := 0;
F2 : R2;
end record;
end Opt1;
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