Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
b41f0b34
Commit
b41f0b34
authored
Jan 13, 2011
by
Michael Meissner
Committed by
Michael Meissner
Jan 13, 2011
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Fix 47251, failure in powerpc -mcpu=power7 -m32 -msoft-float
From-SVN: r168752
parent
29757627
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
30 additions
and
3 deletions
+30
-3
gcc/ChangeLog
+7
-0
gcc/config/rs6000/rs6000.md
+3
-3
gcc/testsuite/ChangeLog
+5
-0
gcc/testsuite/gcc.target/powerpc/pr47251.c
+15
-0
No files found.
gcc/ChangeLog
View file @
b41f0b34
2011-01-13 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/47251
* config/rs6000/rs6000.md (floatunsdidf2): Add check for hardware
floating point.
(floatunsdidf2_fcfidu): Ditto.
2011-01-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
2011-01-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/s390/s390.c (print_operand_address): Replace 'error' with
* config/s390/s390.c (print_operand_address): Replace 'error' with
...
...
gcc/config/rs6000/rs6000.md
View file @
b41f0b34
...
@@ -7167,13 +7167,13 @@
...
@@ -7167,13 +7167,13 @@
[
(set (match_operand:DF 0 "gpc_reg_operand" "")
[
(set (match_operand:DF 0 "gpc_reg_operand" "")
(unsigned_float:DF
(unsigned_float:DF
(match_operand:DI 1 "gpc_reg_operand" "")))]
(match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_
FCFIDU || VECTOR_UNIT_VSX_P (DFmode
)"
"TARGET_
HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode)
)"
"")
"")
(define_insn "
*
floatunsdidf2_fcfidu"
(define_insn "
*
floatunsdidf2_fcfidu"
[
(set (match_operand:DF 0 "gpc_reg_operand" "=d")
[
(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
(unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
"TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
"TARGET_
HARD_FLOAT && TARGET_
FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
"fcfidu %0,%1"
"fcfidu %0,%1"
[
(set_attr "type" "fp")
[
(set_attr "type" "fp")
(set_attr "length" "4")])
(set_attr "length" "4")])
...
@@ -7182,7 +7182,7 @@
...
@@ -7182,7 +7182,7 @@
[
(set (match_operand:DF 0 "gpc_reg_operand" "=d")
[
(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
(unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
(clobber (match_scratch:DI 2 "=d"))]
(clobber (match_scratch:DI 2 "=d"))]
"TARGET_
FCFIDU || VECTOR_UNIT_VSX_P (DFmode
)"
"TARGET_
HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode)
)"
"#"
"#"
"&& reload_completed"
"&& reload_completed"
[
(set (match_dup 2) (match_dup 1))
[
(set (match_dup 2) (match_dup 1))
...
...
gcc/testsuite/ChangeLog
View file @
b41f0b34
2011-01-13 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/47251
* gcc.target/powerpc/pr47251.c: New file, test PR 47251 fix.
2011-01-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
2011-01-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gcc.dg/guality/pr36728-1.c: Disable arg1/2 checks for s390 and
* gcc.dg/guality/pr36728-1.c: Disable arg1/2 checks for s390 and
...
...
gcc/testsuite/gcc.target/powerpc/pr47251.c
0 → 100644
View file @
b41f0b34
/* { dg-do compile { target { powerpc*-*-* && ip32 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-O2 -msoft-float -mcpu=power7" } */
/* PR 47151: libgcc fails to build when using --with-cpu=power7 due to a missed
TARGET_HARD_FLOAT test. */
unsigned
int
__fixunssfdi
(
float
a
)
{
const
float
dfa
=
a
;
const
unsigned
int
hi
=
dfa
/
0x1
p32f
;
const
unsigned
int
lo
=
dfa
-
(
float
)
hi
*
0x1
p32f
;
return
((
unsigned
int
)
hi
<<
(
4
*
8
))
|
lo
;
}
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment