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riscv-gcc-1
Commit b26c8351 by Richard Kenner
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(addsf3, subsf3, mulsf3, divsf3): Put POWERPC first, then POWER. 

From-SVN: r5932
parent 9e88bd1d
Showing with 32 additions and 32 deletions
gcc/config/rs6000/rs6000.md
...@@ -2103,16 +2103,16 @@ ...@@ -2103,16 +2103,16 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fa|fadd} %0,%1,%2" "fadds %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fadds %0,%1,%2" "{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "subsf3" (define_expand "subsf3"
...@@ -2126,16 +2126,16 @@ ...@@ -2126,16 +2126,16 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fs|fsub} %0,%1,%2" "fsubs %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fsubs %0,%1,%2" "{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "mulsf3" (define_expand "mulsf3"
...@@ -2149,16 +2149,16 @@ ...@@ -2149,16 +2149,16 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fm|fmul} %0,%1,%2" "fmuls %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fmuls %0,%1,%2" "{fm|fmul} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "divsf3" (define_expand "divsf3"
...@@ -2172,26 +2172,17 @@ ...@@ -2172,26 +2172,17 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER"
"{fd|fdiv} %0,%1,%2"
[(set_attr "type" "sdiv")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWERPC"
"fdivs %0,%1,%2" "fdivs %0,%1,%2"
[(set_attr "type" "sdiv")]) [(set_attr "type" "sdiv")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f")))]
(match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWER"
"{fma|fmadd} %0,%1,%2,%3" "{fd|fdiv} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "sdiv")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
...@@ -2204,11 +2195,11 @@ ...@@ -2204,11 +2195,11 @@
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWER"
"{fms|fmsub} %0,%1,%2,%3" "{fma|fmadd} %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2222,11 +2213,11 @@ ...@@ -2222,11 +2213,11 @@
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWER"
"{fnma|fnmadd} %0,%1,%2,%3" "{fms|fmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2240,11 +2231,11 @@ ...@@ -2240,11 +2231,11 @@
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWER" "TARGET_POWER"
"{fnms|fnmsub} %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2256,6 +2247,15 @@ ...@@ -2256,6 +2247,15 @@
"fnmsubs %0,%1,%2,%3" "fnmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWER"
"{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_expand "sqrtsf2" (define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
......
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