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riscv-gcc-1
Commit b26c8351 by Richard Kenner
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(addsf3, subsf3, mulsf3, divsf3): Put POWERPC first, then POWER. 

From-SVN: r5932
parent 9e88bd1d
Showing with 32 additions and 32 deletions
gcc/config/rs6000/rs6000.md
...@@ -2103,16 +2103,16 @@ ...@@ -2103,16 +2103,16 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fa|fadd} %0,%1,%2" "fadds %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fadds %0,%1,%2" "{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "subsf3" (define_expand "subsf3"
...@@ -2126,16 +2126,16 @@ ...@@ -2126,16 +2126,16 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fs|fsub} %0,%1,%2" "fsubs %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fsubs %0,%1,%2" "{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "mulsf3" (define_expand "mulsf3"
...@@ -2149,16 +2149,16 @@ ...@@ -2149,16 +2149,16 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fm|fmul} %0,%1,%2" "fmuls %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fmuls %0,%1,%2" "{fm|fmul} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "divsf3" (define_expand "divsf3"
...@@ -2172,16 +2172,16 @@ ...@@ -2172,16 +2172,16 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fd|fdiv} %0,%1,%2" "fdivs %0,%1,%2"
[(set_attr "type" "sdiv")]) [(set_attr "type" "sdiv")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fdivs %0,%1,%2" "{fd|fdiv} %0,%1,%2"
[(set_attr "type" "sdiv")]) [(set_attr "type" "sdiv")])
(define_insn "" (define_insn ""
...@@ -2189,8 +2189,8 @@ ...@@ -2189,8 +2189,8 @@
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fma|fmadd} %0,%1,%2,%3" "fmadds %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2198,8 +2198,8 @@ ...@@ -2198,8 +2198,8 @@
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fmadds %0,%1,%2,%3" "{fma|fmadd} %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2207,8 +2207,8 @@ ...@@ -2207,8 +2207,8 @@
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWER" "TARGET_POWERPC"
"{fms|fmsub} %0,%1,%2,%3" "fmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2216,8 +2216,8 @@ ...@@ -2216,8 +2216,8 @@
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWERPC" "TARGET_POWER"
"fmsubs %0,%1,%2,%3" "{fms|fmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2225,8 +2225,8 @@ ...@@ -2225,8 +2225,8 @@
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWER" "TARGET_POWERPC"
"{fnma|fnmadd} %0,%1,%2,%3" "fnmadds %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2234,8 +2234,8 @@ ...@@ -2234,8 +2234,8 @@
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWERPC" "TARGET_POWER"
"fnmadds %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2243,8 +2243,8 @@ ...@@ -2243,8 +2243,8 @@
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWER" "TARGET_POWERPC"
"{fnms|fnmsub} %0,%1,%2,%3" "fnmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -2252,8 +2252,8 @@ ...@@ -2252,8 +2252,8 @@
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWERPC" "TARGET_POWER"
"fnmsubs %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "sqrtsf2" (define_expand "sqrtsf2"
......
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