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riscv-gcc-1
Commit b24a46be by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: Remove "length 4" from other insns 

There were many insns that set "length 4" explicitly while that does
not make anything clearer to the reader.  So, simplify the code.


	* config/rs6000/altivec.md: Don't set length attribute to the default
	value.
	* config/rs6000/darwin.md: Ditto.
	* config/rs6000/dfp.md: Ditto.
	* config/rs6000/htm.md: Ditto.
	* config/rs6000/rs6000.md: Ditto.
	* config/rs6000/sync.md: Ditto.
	* config/rs6000/vsx.md: Ditto.

From-SVN: r263603
parent a79db151
Showing with 80 additions and 138 deletions
gcc/ChangeLog
2018-08-16 Segher Boessenkool <segher@kernel.crashing.org> 2018-08-16 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Don't set length attribute to the default * config/rs6000/altivec.md: Don't set length attribute to the default
value.
* config/rs6000/darwin.md: Ditto.
* config/rs6000/dfp.md: Ditto.
* config/rs6000/htm.md: Ditto.
* config/rs6000/rs6000.md: Ditto.
* config/rs6000/sync.md: Ditto.
* config/rs6000/vsx.md: Ditto.
2018-08-16 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Don't set length attribute to the default
value, for branch instructions. value, for branch instructions.
* config/rs6000/darwin.md: Ditto. * config/rs6000/darwin.md: Ditto.
* config/rs6000/rs6000.md: Ditto. * config/rs6000/rs6000.md: Ditto.
......
gcc/config/rs6000/altivec.md
...@@ -2042,8 +2042,7 @@ ...@@ -2042,8 +2042,7 @@
"@ "@
vperm %0,%1,%2,%3 vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3" xxperm %x0,%x1,%x3"
[(set_attr "type" "vecperm") [(set_attr "type" "vecperm")])
(set_attr "length" "4")])
(define_insn "altivec_vperm_v8hiv16qi" (define_insn "altivec_vperm_v8hiv16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v,?wo") [(set (match_operand:V16QI 0 "register_operand" "=v,?wo")
...@@ -2055,8 +2054,7 @@ ...@@ -2055,8 +2054,7 @@
"@ "@
vperm %0,%1,%2,%3 vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3" xxperm %x0,%x1,%x3"
[(set_attr "type" "vecperm") [(set_attr "type" "vecperm")])
(set_attr "length" "4")])
(define_expand "altivec_vperm_<mode>_uns" (define_expand "altivec_vperm_<mode>_uns"
[(set (match_operand:VM 0 "register_operand") [(set (match_operand:VM 0 "register_operand")
...@@ -2083,8 +2081,7 @@ ...@@ -2083,8 +2081,7 @@
"@ "@
vperm %0,%1,%2,%3 vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3" xxperm %x0,%x1,%x3"
[(set_attr "type" "vecperm") [(set_attr "type" "vecperm")])
(set_attr "length" "4")])
(define_expand "vec_permv16qi" (define_expand "vec_permv16qi"
[(set (match_operand:V16QI 0 "register_operand") [(set (match_operand:V16QI 0 "register_operand")
...@@ -2110,8 +2107,7 @@ ...@@ -2110,8 +2107,7 @@
"@ "@
vpermr %0,%1,%2,%3 vpermr %0,%1,%2,%3
xxpermr %x0,%x1,%x3" xxpermr %x0,%x1,%x3"
[(set_attr "type" "vecperm") [(set_attr "type" "vecperm")])
(set_attr "length" "4")])
(define_insn "altivec_vrfip" ; ceil (define_insn "altivec_vrfip" ; ceil
[(set (match_operand:V4SF 0 "register_operand" "=v") [(set (match_operand:V4SF 0 "register_operand" "=v")
...@@ -3268,8 +3264,7 @@ ...@@ -3268,8 +3264,7 @@
"@ "@
vperm %0,%1,%2,%3 vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3" xxperm %x0,%x1,%x3"
[(set_attr "type" "vecperm") [(set_attr "type" "vecperm")])
(set_attr "length" "4")])
(define_insn "vperm_v16qiv8hi" (define_insn "vperm_v16qiv8hi"
[(set (match_operand:V8HI 0 "register_operand" "=v,?wo") [(set (match_operand:V8HI 0 "register_operand" "=v,?wo")
...@@ -3281,8 +3276,7 @@ ...@@ -3281,8 +3276,7 @@
"@ "@
vperm %0,%1,%2,%3 vperm %0,%1,%2,%3
xxperm %x0,%x1,%x3" xxperm %x0,%x1,%x3"
[(set_attr "type" "vecperm") [(set_attr "type" "vecperm")])
(set_attr "length" "4")])
(define_expand "vec_unpacku_hi_v16qi" (define_expand "vec_unpacku_hi_v16qi"
...@@ -3857,8 +3851,7 @@ ...@@ -3857,8 +3851,7 @@
(clz:VI2 (match_operand:VI2 1 "register_operand" "v")))] (clz:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P8_VECTOR" "TARGET_P8_VECTOR"
"vclz<wd> %0,%1" "vclz<wd> %0,%1"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
;; Vector absolute difference unsigned ;; Vector absolute difference unsigned
(define_expand "vadu<mode>3" (define_expand "vadu<mode>3"
...@@ -3884,8 +3877,7 @@ ...@@ -3884,8 +3877,7 @@
(ctz:VI2 (match_operand:VI2 1 "register_operand" "v")))] (ctz:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P9_VECTOR" "TARGET_P9_VECTOR"
"vctz<wd> %0,%1" "vctz<wd> %0,%1"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
;; Vector population count ;; Vector population count
(define_insn "*p8v_popcount<mode>2" (define_insn "*p8v_popcount<mode>2"
...@@ -3893,8 +3885,7 @@ ...@@ -3893,8 +3885,7 @@
(popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))] (popcount:VI2 (match_operand:VI2 1 "register_operand" "v")))]
"TARGET_P8_VECTOR" "TARGET_P8_VECTOR"
"vpopcnt<wd> %0,%1" "vpopcnt<wd> %0,%1"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
;; Vector parity ;; Vector parity
(define_insn "*p9v_parity<mode>2" (define_insn "*p9v_parity<mode>2"
...@@ -3902,8 +3893,7 @@ ...@@ -3902,8 +3893,7 @@
(parity:VParity (match_operand:VParity 1 "register_operand" "v")))] (parity:VParity (match_operand:VParity 1 "register_operand" "v")))]
"TARGET_P9_VECTOR" "TARGET_P9_VECTOR"
"vprtyb<wd> %0,%1" "vprtyb<wd> %0,%1"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
;; Vector Gather Bits by Bytes by Doubleword ;; Vector Gather Bits by Bytes by Doubleword
(define_insn "p8v_vgbbd" (define_insn "p8v_vgbbd"
...@@ -3912,8 +3902,7 @@ ...@@ -3912,8 +3902,7 @@
UNSPEC_VGBBD))] UNSPEC_VGBBD))]
"TARGET_P8_VECTOR" "TARGET_P8_VECTOR"
"vgbbd %0,%1" "vgbbd %0,%1"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
;; 128-bit binary integer arithmetic ;; 128-bit binary integer arithmetic
...@@ -3927,8 +3916,7 @@ ...@@ -3927,8 +3916,7 @@
(match_operand:V1TI 2 "register_operand" "v")))] (match_operand:V1TI 2 "register_operand" "v")))]
"TARGET_VADDUQM" "TARGET_VADDUQM"
"vadduqm %0,%1,%2" "vadduqm %0,%1,%2"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddcuq" (define_insn "altivec_vaddcuq"
[(set (match_operand:V1TI 0 "register_operand" "=v") [(set (match_operand:V1TI 0 "register_operand" "=v")
...@@ -3937,8 +3925,7 @@ ...@@ -3937,8 +3925,7 @@
UNSPEC_VADDCUQ))] UNSPEC_VADDCUQ))]
"TARGET_VADDUQM" "TARGET_VADDUQM"
"vaddcuq %0,%1,%2" "vaddcuq %0,%1,%2"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubuqm" (define_insn "altivec_vsubuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v") [(set (match_operand:V1TI 0 "register_operand" "=v")
...@@ -3946,8 +3933,7 @@ ...@@ -3946,8 +3933,7 @@
(match_operand:V1TI 2 "register_operand" "v")))] (match_operand:V1TI 2 "register_operand" "v")))]
"TARGET_VADDUQM" "TARGET_VADDUQM"
"vsubuqm %0,%1,%2" "vsubuqm %0,%1,%2"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubcuq" (define_insn "altivec_vsubcuq"
[(set (match_operand:V1TI 0 "register_operand" "=v") [(set (match_operand:V1TI 0 "register_operand" "=v")
...@@ -3956,8 +3942,7 @@ ...@@ -3956,8 +3942,7 @@
UNSPEC_VSUBCUQ))] UNSPEC_VSUBCUQ))]
"TARGET_VADDUQM" "TARGET_VADDUQM"
"vsubcuq %0,%1,%2" "vsubcuq %0,%1,%2"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddeuqm" (define_insn "altivec_vaddeuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v") [(set (match_operand:V1TI 0 "register_operand" "=v")
...@@ -3967,8 +3952,7 @@ ...@@ -3967,8 +3952,7 @@
UNSPEC_VADDEUQM))] UNSPEC_VADDEUQM))]
"TARGET_VADDUQM" "TARGET_VADDUQM"
"vaddeuqm %0,%1,%2,%3" "vaddeuqm %0,%1,%2,%3"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddecuq" (define_insn "altivec_vaddecuq"
[(set (match_operand:V1TI 0 "register_operand" "=v") [(set (match_operand:V1TI 0 "register_operand" "=v")
...@@ -3978,8 +3962,7 @@ ...@@ -3978,8 +3962,7 @@
UNSPEC_VADDECUQ))] UNSPEC_VADDECUQ))]
"TARGET_VADDUQM" "TARGET_VADDUQM"
"vaddecuq %0,%1,%2,%3" "vaddecuq %0,%1,%2,%3"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubeuqm" (define_insn "altivec_vsubeuqm"
[(set (match_operand:V1TI 0 "register_operand" "=v") [(set (match_operand:V1TI 0 "register_operand" "=v")
...@@ -3989,8 +3972,7 @@ ...@@ -3989,8 +3972,7 @@
UNSPEC_VSUBEUQM))] UNSPEC_VSUBEUQM))]
"TARGET_VADDUQM" "TARGET_VADDUQM"
"vsubeuqm %0,%1,%2,%3" "vsubeuqm %0,%1,%2,%3"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubecuq" (define_insn "altivec_vsubecuq"
[(set (match_operand:V1TI 0 "register_operand" "=v") [(set (match_operand:V1TI 0 "register_operand" "=v")
...@@ -4000,8 +3982,7 @@ ...@@ -4000,8 +3982,7 @@
UNSPEC_VSUBECUQ))] UNSPEC_VSUBECUQ))]
"TARGET_VADDUQM" "TARGET_VADDUQM"
"vsubecuq %0,%1,%2,%3" "vsubecuq %0,%1,%2,%3"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
;; We use V2DI as the output type to simplify converting the permute ;; We use V2DI as the output type to simplify converting the permute
;; bits into an integer ;; bits into an integer
...@@ -4093,8 +4074,7 @@ ...@@ -4093,8 +4074,7 @@
(clobber (reg:CCFP CR6_REGNO))] (clobber (reg:CCFP CR6_REGNO))]
"TARGET_P8_VECTOR" "TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3" "bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we ;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we
;; can use the unordered test for BCD nans and add/subtracts that overflow. An ;; can use the unordered test for BCD nans and add/subtracts that overflow. An
...@@ -4112,8 +4092,7 @@ ...@@ -4112,8 +4092,7 @@
(clobber (match_scratch:V1TI 0 "=v"))] (clobber (match_scratch:V1TI 0 "=v"))]
"TARGET_P8_VECTOR" "TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3" "bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "*bcd<bcd_add_sub>_test2" (define_insn "*bcd<bcd_add_sub>_test2"
[(set (match_operand:V1TI 0 "register_operand" "=v") [(set (match_operand:V1TI 0 "register_operand" "=v")
...@@ -4130,8 +4109,7 @@ ...@@ -4130,8 +4109,7 @@
(match_operand:V2DF 4 "zero_constant" "j")))] (match_operand:V2DF 4 "zero_constant" "j")))]
"TARGET_P8_VECTOR" "TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3" "bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "length" "4") [(set_attr "type" "vecsimple")])
(set_attr "type" "vecsimple")])
(define_insn "darn_32" (define_insn "darn_32"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
......
gcc/config/rs6000/darwin.md
...@@ -23,8 +23,7 @@ You should have received a copy of the GNU General Public License ...@@ -23,8 +23,7 @@ You should have received a copy of the GNU General Public License
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b") (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(high:DI (match_operand 2 "" ""))))] (high:DI (match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_64BIT" "TARGET_MACHO && TARGET_64BIT"
"addis %0,%1,ha16(%2)" "addis %0,%1,ha16(%2)")
[(set_attr "length" "4")])
(define_insn "movdf_low_si" (define_insn "movdf_low_si"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
...@@ -72,8 +71,7 @@ You should have received a copy of the GNU General Public License ...@@ -72,8 +71,7 @@ You should have received a copy of the GNU General Public License
gcc_unreachable (); gcc_unreachable ();
} }
} }
[(set_attr "type" "load") [(set_attr "type" "load")])
(set_attr "length" "4,4")])
(define_insn "movdf_low_st_si" (define_insn "movdf_low_st_si"
[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
...@@ -81,8 +79,7 @@ You should have received a copy of the GNU General Public License ...@@ -81,8 +79,7 @@ You should have received a copy of the GNU General Public License
(match_operand:DF 0 "gpc_reg_operand" "f"))] (match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"stfd %0,lo16(%2)(%1)" "stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store") [(set_attr "type" "store")])
(set_attr "length" "4")])
(define_insn "movdf_low_st_di" (define_insn "movdf_low_st_di"
[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
...@@ -90,8 +87,7 @@ You should have received a copy of the GNU General Public License ...@@ -90,8 +87,7 @@ You should have received a copy of the GNU General Public License
(match_operand:DF 0 "gpc_reg_operand" "f"))] (match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT" "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"stfd %0,lo16(%2)(%1)" "stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store") [(set_attr "type" "store")])
(set_attr "length" "4")])
(define_insn "movsf_low_si" (define_insn "movsf_low_si"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
...@@ -101,8 +97,7 @@ You should have received a copy of the GNU General Public License ...@@ -101,8 +97,7 @@ You should have received a copy of the GNU General Public License
"@ "@
lfs %0,lo16(%2)(%1) lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)" lwz %0,lo16(%2)(%1)"
[(set_attr "type" "load") [(set_attr "type" "load")])
(set_attr "length" "4")])
(define_insn "movsf_low_di" (define_insn "movsf_low_di"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
...@@ -112,8 +107,7 @@ You should have received a copy of the GNU General Public License ...@@ -112,8 +107,7 @@ You should have received a copy of the GNU General Public License
"@ "@
lfs %0,lo16(%2)(%1) lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)" lwz %0,lo16(%2)(%1)"
[(set_attr "type" "load") [(set_attr "type" "load")])
(set_attr "length" "4")])
(define_insn "movsf_low_st_si" (define_insn "movsf_low_st_si"
[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
...@@ -123,8 +117,7 @@ You should have received a copy of the GNU General Public License ...@@ -123,8 +117,7 @@ You should have received a copy of the GNU General Public License
"@ "@
stfs %0,lo16(%2)(%1) stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)" stw %0,lo16(%2)(%1)"
[(set_attr "type" "store") [(set_attr "type" "store")])
(set_attr "length" "4")])
(define_insn "movsf_low_st_di" (define_insn "movsf_low_st_di"
[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
...@@ -134,8 +127,7 @@ You should have received a copy of the GNU General Public License ...@@ -134,8 +127,7 @@ You should have received a copy of the GNU General Public License
"@ "@
stfs %0,lo16(%2)(%1) stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)" stw %0,lo16(%2)(%1)"
[(set_attr "type" "store") [(set_attr "type" "store")])
(set_attr "length" "4")])
;; 64-bit MachO load/store support ;; 64-bit MachO load/store support
(define_insn "movdi_low" (define_insn "movdi_low"
...@@ -146,8 +138,7 @@ You should have received a copy of the GNU General Public License ...@@ -146,8 +138,7 @@ You should have received a copy of the GNU General Public License
"@ "@
ld %0,lo16(%2)(%1) ld %0,lo16(%2)(%1)
lfd %0,lo16(%2)(%1)" lfd %0,lo16(%2)(%1)"
[(set_attr "type" "load") [(set_attr "type" "load")])
(set_attr "length" "4")])
(define_insn "movsi_low_st" (define_insn "movsi_low_st"
[(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
...@@ -155,8 +146,7 @@ You should have received a copy of the GNU General Public License ...@@ -155,8 +146,7 @@ You should have received a copy of the GNU General Public License
(match_operand:SI 0 "gpc_reg_operand" "r"))] (match_operand:SI 0 "gpc_reg_operand" "r"))]
"TARGET_MACHO && ! TARGET_64BIT" "TARGET_MACHO && ! TARGET_64BIT"
"stw %0,lo16(%2)(%1)" "stw %0,lo16(%2)(%1)"
[(set_attr "type" "store") [(set_attr "type" "store")])
(set_attr "length" "4")])
(define_insn "movdi_low_st" (define_insn "movdi_low_st"
[(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
...@@ -166,8 +156,7 @@ You should have received a copy of the GNU General Public License ...@@ -166,8 +156,7 @@ You should have received a copy of the GNU General Public License
"@ "@
std %0,lo16(%2)(%1) std %0,lo16(%2)(%1)
stfd %0,lo16(%2)(%1)" stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store") [(set_attr "type" "store")])
(set_attr "length" "4")])
;; Mach-O PIC trickery. ;; Mach-O PIC trickery.
(define_expand "macho_high" (define_expand "macho_high"
......
gcc/config/rs6000/dfp.md
...@@ -37,8 +37,7 @@ ...@@ -37,8 +37,7 @@
|| gpc_reg_operand (operands[1], SDmode)) || gpc_reg_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT" && TARGET_HARD_FLOAT"
"stfd%U0%X0 %1,%0" "stfd%U0%X0 %1,%0"
[(set_attr "type" "fpstore") [(set_attr "type" "fpstore")])
(set_attr "length" "4")])
(define_insn "movsd_load" (define_insn "movsd_load"
[(set (match_operand:SD 0 "nonimmediate_operand" "=f") [(set (match_operand:SD 0 "nonimmediate_operand" "=f")
...@@ -48,8 +47,7 @@ ...@@ -48,8 +47,7 @@
|| gpc_reg_operand (operands[1], DDmode)) || gpc_reg_operand (operands[1], DDmode))
&& TARGET_HARD_FLOAT" && TARGET_HARD_FLOAT"
"lfd%U1%X1 %0,%1" "lfd%U1%X1 %0,%1"
[(set_attr "type" "fpload") [(set_attr "type" "fpload")])
(set_attr "length" "4")])
;; Hardware support for decimal floating point operations. ;; Hardware support for decimal floating point operations.
......
gcc/config/rs6000/htm.md
...@@ -72,8 +72,7 @@ ...@@ -72,8 +72,7 @@
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"tabort. %0" "tabort. %0"
[(set_attr "type" "htmsimple") [(set_attr "type" "htmsimple")])
(set_attr "length" "4")])
(define_expand "tabort<wd>c" (define_expand "tabort<wd>c"
[(parallel [(parallel
...@@ -98,8 +97,7 @@ ...@@ -98,8 +97,7 @@
(set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"tabort<wd>c. %0,%1,%2" "tabort<wd>c. %0,%1,%2"
[(set_attr "type" "htmsimple") [(set_attr "type" "htmsimple")])
(set_attr "length" "4")])
(define_expand "tabort<wd>ci" (define_expand "tabort<wd>ci"
[(parallel [(parallel
...@@ -124,8 +122,7 @@ ...@@ -124,8 +122,7 @@
(set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"tabort<wd>ci. %0,%1,%2" "tabort<wd>ci. %0,%1,%2"
[(set_attr "type" "htmsimple") [(set_attr "type" "htmsimple")])
(set_attr "length" "4")])
(define_expand "tbegin" (define_expand "tbegin"
[(parallel [(parallel
...@@ -146,8 +143,7 @@ ...@@ -146,8 +143,7 @@
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"tbegin. %0" "tbegin. %0"
[(set_attr "type" "htm") [(set_attr "type" "htm")])
(set_attr "length" "4")])
(define_expand "tcheck" (define_expand "tcheck"
[(parallel [(parallel
...@@ -166,8 +162,7 @@ ...@@ -166,8 +162,7 @@
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"tcheck %0" "tcheck %0"
[(set_attr "type" "htm") [(set_attr "type" "htm")])
(set_attr "length" "4")])
(define_expand "tend" (define_expand "tend"
[(parallel [(parallel
...@@ -188,8 +183,7 @@ ...@@ -188,8 +183,7 @@
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"tend. %0" "tend. %0"
[(set_attr "type" "htm") [(set_attr "type" "htm")])
(set_attr "length" "4")])
(define_expand "trechkpt" (define_expand "trechkpt"
[(parallel [(parallel
...@@ -208,8 +202,7 @@ ...@@ -208,8 +202,7 @@
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"trechkpt." "trechkpt."
[(set_attr "type" "htmsimple") [(set_attr "type" "htmsimple")])
(set_attr "length" "4")])
(define_expand "treclaim" (define_expand "treclaim"
[(parallel [(parallel
...@@ -230,8 +223,7 @@ ...@@ -230,8 +223,7 @@
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"treclaim. %0" "treclaim. %0"
[(set_attr "type" "htmsimple") [(set_attr "type" "htmsimple")])
(set_attr "length" "4")])
(define_expand "tsr" (define_expand "tsr"
[(parallel [(parallel
...@@ -252,8 +244,7 @@ ...@@ -252,8 +244,7 @@
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"tsr. %0" "tsr. %0"
[(set_attr "type" "htmsimple") [(set_attr "type" "htmsimple")])
(set_attr "length" "4")])
(define_expand "ttest" (define_expand "ttest"
[(parallel [(parallel
...@@ -272,8 +263,7 @@ ...@@ -272,8 +263,7 @@
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))] (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM" "TARGET_HTM"
"tabortwci. 0,1,0" "tabortwci. 0,1,0"
[(set_attr "type" "htmsimple") [(set_attr "type" "htmsimple")])
(set_attr "length" "4")])
(define_insn "htm_mfspr_<mode>" (define_insn "htm_mfspr_<mode>"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r") [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
...@@ -282,8 +272,7 @@ ...@@ -282,8 +272,7 @@
UNSPECV_HTM_MFSPR))] UNSPECV_HTM_MFSPR))]
"TARGET_HTM" "TARGET_HTM"
"mfspr %0,%1"; "mfspr %0,%1";
[(set_attr "type" "htm") [(set_attr "type" "htm")])
(set_attr "length" "4")])
(define_insn "htm_mtspr_<mode>" (define_insn "htm_mtspr_<mode>"
[(set (match_operand:GPR 2 "htm_spr_reg_operand" "") [(set (match_operand:GPR 2 "htm_spr_reg_operand" "")
...@@ -292,5 +281,4 @@ ...@@ -292,5 +281,4 @@
UNSPECV_HTM_MTSPR))] UNSPECV_HTM_MTSPR))]
"TARGET_HTM" "TARGET_HTM"
"mtspr %1,%0"; "mtspr %1,%0";
[(set_attr "type" "htm") [(set_attr "type" "htm")])
(set_attr "length" "4")])
gcc/config/rs6000/rs6000.md
...@@ -2378,8 +2378,7 @@ ...@@ -2378,8 +2378,7 @@
(bswap:HSI (match_operand:HSI 1 "memory_operand" "Z"))))] (bswap:HSI (match_operand:HSI 1 "memory_operand" "Z"))))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"l<wd>brx %0,%y1" "l<wd>brx %0,%y1"
[(set_attr "length" "4") [(set_attr "type" "load")])
(set_attr "type" "load")])
(define_insn "*bswaphi2_extendsi" (define_insn "*bswaphi2_extendsi"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -2387,8 +2386,7 @@ ...@@ -2387,8 +2386,7 @@
(bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))] (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
"" ""
"lhbrx %0,%y1" "lhbrx %0,%y1"
[(set_attr "length" "4") [(set_attr "type" "load")])
(set_attr "type" "load")])
;; Separate the bswap patterns into load, store, and gpr<-gpr. This prevents ;; Separate the bswap patterns into load, store, and gpr<-gpr. This prevents
;; the register allocator from converting a gpr<-gpr swap into a store and then ;; the register allocator from converting a gpr<-gpr swap into a store and then
...@@ -6080,8 +6078,7 @@ ...@@ -6080,8 +6078,7 @@
"@ "@
fcfidu %0,%1 fcfidu %0,%1
xscvuxddp %x0,%x1" xscvuxddp %x0,%x1"
[(set_attr "type" "fp") [(set_attr "type" "fp")])
(set_attr "length" "4")])
(define_insn_and_split "*floatunsdidf2_mem" (define_insn_and_split "*floatunsdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
...@@ -6696,8 +6693,7 @@ ...@@ -6696,8 +6693,7 @@
(match_operand 2 "" ""))))] (match_operand 2 "" ""))))]
"TARGET_MACHO && ! TARGET_64BIT" "TARGET_MACHO && ! TARGET_64BIT"
"lwz %0,lo16(%2)(%1)" "lwz %0,lo16(%2)(%1)"
[(set_attr "type" "load") [(set_attr "type" "load")])
(set_attr "length" "4")])
;; MR LA LWZ LFIWZX LXSIWZX ;; MR LA LWZ LFIWZX LXSIWZX
;; STW STFIWX STXSIWX LI LIS ;; STW STFIWX STXSIWX LI LIS
...@@ -9407,8 +9403,7 @@ ...@@ -9407,8 +9403,7 @@
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGD)))] UNSPEC_TLSGD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
"addis %0,%1,%2@got@tlsgd@ha" "addis %0,%1,%2@got@tlsgd@ha")
[(set_attr "length" "4")])
(define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>" (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
...@@ -9417,8 +9412,7 @@ ...@@ -9417,8 +9412,7 @@
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGD)))] UNSPEC_TLSGD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
"addi %0,%1,%2@got@tlsgd@l" "addi %0,%1,%2@got@tlsgd@l")
[(set_attr "length" "4")])
(define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>" (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
...@@ -9542,8 +9536,7 @@ ...@@ -9542,8 +9536,7 @@
(match_operand:TLSmode 1 "gpc_reg_operand" "b")] (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
UNSPEC_TLSLD)))] UNSPEC_TLSLD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
"addis %0,%1,%&@got@tlsld@ha" "addis %0,%1,%&@got@tlsld@ha")
[(set_attr "length" "4")])
(define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>" (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
...@@ -9552,8 +9545,7 @@ ...@@ -9552,8 +9545,7 @@
(match_operand:TLSmode 2 "gpc_reg_operand" "b")] (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
UNSPEC_TLSLD)))] UNSPEC_TLSLD)))]
"HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
"addi %0,%1,%&@got@tlsld@l" "addi %0,%1,%&@got@tlsld@l")
[(set_attr "length" "4")])
(define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>" (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
...@@ -9638,8 +9630,7 @@ ...@@ -9638,8 +9630,7 @@
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGOTDTPREL)))] UNSPEC_TLSGOTDTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
"addis %0,%1,%2@got@dtprel@ha" "addis %0,%1,%2@got@dtprel@ha")
[(set_attr "length" "4")])
(define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>" (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
...@@ -9648,8 +9639,7 @@ ...@@ -9648,8 +9639,7 @@
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGOTDTPREL)))] UNSPEC_TLSGOTDTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
"l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)" "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)")
[(set_attr "length" "4")])
(define_insn "tls_tprel_<TLSmode:tls_abi_suffix>" (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
...@@ -9707,8 +9697,7 @@ ...@@ -9707,8 +9697,7 @@
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGOTTPREL)))] UNSPEC_TLSGOTTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
"addis %0,%1,%2@got@tprel@ha" "addis %0,%1,%2@got@tprel@ha")
[(set_attr "length" "4")])
(define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>" (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
...@@ -9717,8 +9706,7 @@ ...@@ -9717,8 +9706,7 @@
(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
UNSPEC_TLSGOTTPREL)))] UNSPEC_TLSGOTTPREL)))]
"HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
"l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)" "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)")
[(set_attr "length" "4")])
(define_insn "tls_tls_<TLSmode:tls_abi_suffix>" (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
[(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
...@@ -11098,8 +11086,7 @@ ...@@ -11098,8 +11086,7 @@
(set (attr "indexed") (set (attr "indexed")
(if_then_else (match_operand 0 "indexed_address_mem") (if_then_else (match_operand 0 "indexed_address_mem")
(const_string "yes") (const_string "yes")
(const_string "no"))) (const_string "no")))])
(set_attr "length" "4")])
(define_insn "probe_stack_range<P:mode>" (define_insn "probe_stack_range<P:mode>"
[(set (match_operand:P 0 "register_operand" "=&r") [(set (match_operand:P 0 "register_operand" "=&r")
...@@ -12347,8 +12334,7 @@ ...@@ -12347,8 +12334,7 @@
{ {
return output_cbranch (operands[0], NULL, 0, insn); return output_cbranch (operands[0], NULL, 0, insn);
} }
[(set_attr "type" "jmpreg") [(set_attr "type" "jmpreg")])
(set_attr "length" "4")])
;; Logic on condition register values. ;; Logic on condition register values.
...@@ -13859,8 +13845,7 @@ ...@@ -13859,8 +13845,7 @@
UNSPEC_ADDG6S))] UNSPEC_ADDG6S))]
"TARGET_POPCNTD" "TARGET_POPCNTD"
"addg6s %0,%1,%2" "addg6s %0,%1,%2"
[(set_attr "type" "integer") [(set_attr "type" "integer")])
(set_attr "length" "4")])
(define_insn "cdtbcd" (define_insn "cdtbcd"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -13868,8 +13853,7 @@ ...@@ -13868,8 +13853,7 @@
UNSPEC_CDTBCD))] UNSPEC_CDTBCD))]
"TARGET_POPCNTD" "TARGET_POPCNTD"
"cdtbcd %0,%1" "cdtbcd %0,%1"
[(set_attr "type" "integer") [(set_attr "type" "integer")])
(set_attr "length" "4")])
(define_insn "cbcdtd" (define_insn "cbcdtd"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -13877,8 +13861,7 @@ ...@@ -13877,8 +13861,7 @@
UNSPEC_CBCDTD))] UNSPEC_CBCDTD))]
"TARGET_POPCNTD" "TARGET_POPCNTD"
"cbcdtd %0,%1" "cbcdtd %0,%1"
[(set_attr "type" "integer") [(set_attr "type" "integer")])
(set_attr "length" "4")])
(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
UNSPEC_DIVEU]) UNSPEC_DIVEU])
...@@ -13935,8 +13918,7 @@ ...@@ -13935,8 +13918,7 @@
operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno); operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
} }
[(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store") [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")])
(set_attr "length" "4")])
(define_insn_and_split "unpack<mode>_nodm" (define_insn_and_split "unpack<mode>_nodm"
[(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m") [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
...@@ -13959,8 +13941,7 @@ ...@@ -13959,8 +13941,7 @@
operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno); operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
} }
[(set_attr "type" "fp,fpstore") [(set_attr "type" "fp,fpstore")])
(set_attr "length" "4")])
(define_insn_and_split "pack<mode>" (define_insn_and_split "pack<mode>"
[(set (match_operand:FMOVE128 0 "register_operand" "=&d") [(set (match_operand:FMOVE128 0 "register_operand" "=&d")
......
gcc/config/rs6000/sync.md
...@@ -132,8 +132,7 @@ ...@@ -132,8 +132,7 @@
"TARGET_SYNC_TI "TARGET_SYNC_TI
&& !reg_mentioned_p (operands[0], operands[1])" && !reg_mentioned_p (operands[0], operands[1])"
"lq %0,%1" "lq %0,%1"
[(set_attr "type" "load") [(set_attr "type" "load")])
(set_attr "length" "4")])
(define_expand "atomic_load<mode>" (define_expand "atomic_load<mode>"
[(set (match_operand:AINT 0 "register_operand") ;; output [(set (match_operand:AINT 0 "register_operand") ;; output
...@@ -196,8 +195,7 @@ ...@@ -196,8 +195,7 @@
[(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))] [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]
"TARGET_SYNC_TI" "TARGET_SYNC_TI"
"stq %1,%0" "stq %1,%0"
[(set_attr "type" "store") [(set_attr "type" "store")])
(set_attr "length" "4")])
(define_expand "atomic_store<mode>" (define_expand "atomic_store<mode>"
[(set (match_operand:AINT 0 "memory_operand") ;; memory [(set (match_operand:AINT 0 "memory_operand") ;; memory
......
gcc/config/rs6000/vsx.md
...@@ -3267,8 +3267,7 @@ ...@@ -3267,8 +3267,7 @@
stfd%U0%X0 %1,%0 stfd%U0%X0 %1,%0
stxsd%U0x %x1,%y0 stxsd%U0x %x1,%y0
stxsd %1,%0" stxsd %1,%0"
[(set_attr "type" "fpstore") [(set_attr "type" "fpstore")])
(set_attr "length" "4")])
;; Variable V2DI/V2DF extract shift ;; Variable V2DI/V2DF extract shift
(define_insn "vsx_vslo_<mode>" (define_insn "vsx_vslo_<mode>"
......
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