mips.md (type): Add logical, signext and move.

2007-07-04  David Ung  <davidu@mips.com>
            Joseph Myers  <joseph@codesourcery.com>

	* config/mips/mips.md (type): Add logical, signext and move.
	(one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3,
	*ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16,
	*nor<mode>3, "Combiner patterns to optimize truncate/zero_extend
	combinations", *zero_extend<SHORT:mode><GPR:mode>2,
	*zero_extendqihi2, *extend<SHORT:mode><GPR:mode>2_mips16e,
	*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>, *movdi_64bit,
	*movdi_64bit_mips16, *movsi_internal, *movsi_mips16, movcc,
	*movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16,
	*movsf_hardfloat, *movsf_softfloat, *movsf_mips16,
	*movdf_hardfloat_64bit, *movdf_hardfloat_32bit,
	movv2sf_hardfloat_64bit): Use the new types.
	(*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16,
	*movdf_softfloat, *movdf_mips16): Use "multi".
	(extendqihi2): Replace with a define_expand.
	(*extendqihi2_mips16e, *extendqihi2, *extendqihi2_seb): New.
	Based on extend<SHORT:mode><GPR:mode>2 patterns.
	* config/mips/74k.md (r74k_int_logical): New reservation and
	bypasses.
	(r74k_int_arith): Remove "slt".
	* config/mips/24k.md, config/mips/4130.md, config/mips/4k.md,
	config/mips/5400.md, config/mips/5500.md, config/mips/5k.md,
	config/mips/7000.md, config/mips/9000.md, config/mips/generic.md,
	config/mips/sb1.md, config/mips/sr71k.md: Add new types to
	reservations for "arith".

Co-Authored-By: Joseph Myers <joseph@codesourcery.com>

From-SVN: r126327

gcc/ChangeLog

+2007-07-04  David Ung  <davidu@mips.com>
+            Joseph Myers  <joseph@codesourcery.com>
+
+	* config/mips/mips.md (type): Add logical, signext and move.
+	(one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3,
+	*ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16,
+	*nor<mode>3, "Combiner patterns to optimize truncate/zero_extend
+	combinations", *zero_extend<SHORT:mode><GPR:mode>2,
+	*zero_extendqihi2, *extend<SHORT:mode><GPR:mode>2_mips16e,
+	*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>, *movdi_64bit,
+	*movdi_64bit_mips16, *movsi_internal, *movsi_mips16, movcc,
+	*movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16,
+	*movsf_hardfloat, *movsf_softfloat, *movsf_mips16,
+	*movdf_hardfloat_64bit, *movdf_hardfloat_32bit,
+	movv2sf_hardfloat_64bit): Use the new types.
+	(*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16,
+	*movdf_softfloat, *movdf_mips16): Use "multi".
+	(extendqihi2): Replace with a define_expand.
+	(*extendqihi2_mips16e, *extendqihi2, *extendqihi2_seb): New.
+	Based on extend<SHORT:mode><GPR:mode>2 patterns.
+	* config/mips/74k.md (r74k_int_logical): New reservation and
+	bypasses.
+	(r74k_int_arith): Remove "slt".
+	* config/mips/24k.md, config/mips/4130.md, config/mips/4k.md,
+	config/mips/5400.md, config/mips/5500.md, config/mips/5k.md,
+	config/mips/7000.md, config/mips/9000.md, config/mips/generic.md,
+	config/mips/sb1.md, config/mips/sr71k.md: Add new types to
+	reservations for "arith".
+
 2007-07-04  Richard Guenther  <rguenther@suse.de>
 
 	* tree-ssa.c (useless_type_conversion_p): Add handling for

gcc/config/mips/24k.md

@@ -55,7 +55,7 @@
 ;;  differentiate between integer/float moves)
 (define_insn_reservation "r24k_int_arith" 1
   (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (eq_attr "type" "arith,const,nop,shift,slt"))
+       (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
   "r24k_iss+r24k_ixu_arith")
 
 

gcc/config/mips/4130.md

@@ -66,7 +66,7 @@
 
 (define_insn_reservation "vr4130_int" 1
   (and (eq_attr "cpu" "r4130")
-       (eq_attr "type" "const,arith,shift,slt,nop"))
+       (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
   "vr4130_alu1 | vr4130_alu2")
 
 (define_insn_reservation "vr4130_load" 3

gcc/config/mips/4k.md

@@ -127,7 +127,7 @@
 ;; All other integer insns.
 (define_insn_reservation "r4k_int_alu" 1
   (and (eq_attr "cpu" "4kc,4kp")
-       (eq_attr "type" "arith,condmove,shift,const,nop,slt"))
+       (eq_attr "type" "arith,condmove,const,logical,move,nop,shift,signext,slt"))
   "r4k_ixu_arith")
 
 (define_insn_reservation "r4k_int_branch" 1

gcc/config/mips/5400.md

@@ -60,7 +60,7 @@
 
 (define_insn_reservation "ir_vr54_arith" 1
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
+       (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_imul_si" 3

gcc/config/mips/5500.md

@@ -56,7 +56,7 @@
 
 (define_insn_reservation "ir_vr55_arith" 1
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
+       (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
   "vr55_dp0|vr55_dp1")
 
 (define_bypass 2

gcc/config/mips/5k.md

@@ -101,7 +101,7 @@
 ;; All other integer insns.
 (define_insn_reservation "r5k_int_alu" 1
   (and (eq_attr "cpu" "5kc,5kf")
-       (eq_attr "type" "arith,condmove,shift,const,nop,slt"))
+       (eq_attr "type" "arith,condmove,const,logical,move,nop,shift,signext,slt"))
   "r5k_ixu_arith")
 
 (define_insn_reservation "r5k_int_branch" 1

gcc/config/mips/7000.md

@@ -88,7 +88,7 @@
 
 (define_insn_reservation "rm7_int_other" 1
   (and (eq_attr "cpu" "r7000")
-       (eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
+       (eq_attr "type" "arith,shift,signext,slt,clz,const,condmove,logical,move,nop,trap"))
   "rm7_iaddsub")
 
 (define_insn_reservation "rm7_ld" 2

gcc/config/mips/74k.md

@@ -35,13 +35,18 @@
 ;; Producers
 ;; --------------------------------------------------------------
 
-;; Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
-;;    ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
-;;    sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
-;;    xor, xori
+;; ALU: Logicals/Arithmetics
+;; - Logicals, move (addu/addiu with rt = 0), Set less than, 
+;;   sign extend - 1 cycle
+(define_insn_reservation "r74k_int_logical" 1
+  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
+       (eq_attr "type" "logical,move,signext,slt"))
+  "r74k_alu")
+
+;; - Arithmetics - 2 cycles
 (define_insn_reservation "r74k_int_arith" 2
   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
-       (eq_attr "type" "arith,const,shift,slt,clz"))
+       (eq_attr "type" "arith,const,shift,clz"))
   "r74k_alu")
 
 (define_insn_reservation "r74k_int_nop" 0
@@ -137,6 +142,12 @@
 (define_bypass 4 "r74k_int_load" "r74k_int_load")
 (define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")
 
+;; logical/move/slt/signext->next use :  1 cycles (Default)
+;; logical/move/slt/signext->load base:  2 cycles
+;; logical/move/slt/signext->store base: 2 cycles
+(define_bypass 2 "r74k_int_logical" "r74k_int_load")
+(define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")
+
 ;; arith->next use :  2 cycles (Default)
 ;; arith->load base:  3 cycles
 ;; arith->store base: 3 cycles

gcc/config/mips/9000.md

@@ -52,7 +52,7 @@
 
 (define_insn_reservation "rm9k_int" 1
   (and (eq_attr "cpu" "r9000")
-       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
+       (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
   "rm9k_any1 | rm9k_any2")
 
 (define_insn_reservation "rm9k_int_cmove" 2

gcc/config/mips/generic.md

@@ -24,7 +24,7 @@
 
 (define_insn_reservation "generic_alu" 1
   (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith,
-		   shift,slt,clz,trap,multi,nop")
+		   shift,slt,clz,trap,multi,nop,logical,signext,move")
   "alu")
 
 (define_insn_reservation "generic_load" 3

gcc/config/mips/sb1.md

@@ -236,7 +236,7 @@
 
 (define_insn_reservation "ir_sb1_simple_alu" 2
   (and (eq_attr "cpu" "sb1")
-       (eq_attr "type" "const,arith"))
+       (eq_attr "type" "const,arith,logical,move,signext"))
   "sb1_ls1 | sb1_ex1 | sb1_ex0")
 
 ;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we
@@ -244,7 +244,7 @@
 
 (define_insn_reservation "ir_sb1a_simple_alu" 1
   (and (eq_attr "cpu" "sb1a")
-       (eq_attr "type" "const,arith"))
+       (eq_attr "type" "const,arith,logical,move,signext"))
   "sb1_ex1 | sb1_ex0")
 
 ;; ??? condmove also includes some FP instructions that execute on the FP

gcc/config/mips/sr71k.md

@@ -188,7 +188,7 @@
 
 (define_insn_reservation "ir_sr70_arith" 1
   (and (eq_attr "cpu" "sr71000")
-       (eq_attr "type" "arith,shift,slt,clz,const,trap"))
+       (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,trap"))
   "ri_insns")
 
 ;; emulate repeat (dispatch stall) by spending extra cycle(s) in