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Commit b187677b by Richard Sandiford Committed by Richard Sandiford
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[AArch64] Rewrite aarch64_simd_valid_immediate 

This patch reworks aarch64_simd_valid_immediate so that
it's easier to add SVE support.  The main changes are:

- make simd_immediate_info easier to construct
- replace the while (1) { ... break; } blocks with checks that use
  the full 64-bit value of the constant
- treat floating-point modes as integers if they aren't valid
  as floating-point values

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_output_simd_mov_immediate):
	Remove the mode argument.
	(aarch64_simd_valid_immediate): Remove the mode and inverse
	arguments.
	* config/aarch64/iterators.md (bitsize): New iterator.
	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>, and<mode>3)
	(ior<mode>3): Update calls to aarch64_output_simd_mov_immediate.
	* config/aarch64/constraints.md (Do, Db, Dn): Update calls to
	aarch64_simd_valid_immediate.
	* config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Likewise.
	(aarch64_reg_or_bic_imm): Likewise.
	* config/aarch64/aarch64.c (simd_immediate_info): Replace mvn
	with an insn_type enum and msl with a modifier_type enum.
	Replace element_width with a scalar_mode.  Change the shift
	to unsigned int.  Add constructors for scalar_float_mode and
	scalar_int_mode elements.
	(aarch64_vect_float_const_representable_p): Delete.
	(aarch64_can_const_movi_rtx_p)
	(aarch64_simd_scalar_immediate_valid_for_move)
	(aarch64_simd_make_constant): Update call to
	aarch64_simd_valid_immediate.
	(aarch64_advsimd_valid_immediate_hs): New function.
	(aarch64_advsimd_valid_immediate): Likewise.
	(aarch64_simd_valid_immediate): Remove mode and inverse
	arguments.  Rewrite to use the above.  Use const_vec_duplicate_p
	to detect duplicated constants and use aarch64_float_const_zero_rtx_p
	and aarch64_float_const_representable_p on the result.
	(aarch64_output_simd_mov_immediate): Remove mode argument.
	Update call to aarch64_simd_valid_immediate and use of
	simd_immediate_info.
	(aarch64_output_scalar_simd_mov_immediate): Update call
	accordingly.

gcc/testsuite/
	* gcc.target/aarch64/vect-movi.c (movi_float_lsl24): New function.
	(main): Call it.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256205
parent c6561a1a
Showing with 82 additions and 20 deletions
gcc/ChangeLog
......@@ -2,6 +2,43 @@
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_output_simd_mov_immediate):
Remove the mode argument.
(aarch64_simd_valid_immediate): Remove the mode and inverse
arguments.
* config/aarch64/iterators.md (bitsize): New iterator.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>, and<mode>3)
(ior<mode>3): Update calls to aarch64_output_simd_mov_immediate.
* config/aarch64/constraints.md (Do, Db, Dn): Update calls to
aarch64_simd_valid_immediate.
* config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Likewise.
(aarch64_reg_or_bic_imm): Likewise.
* config/aarch64/aarch64.c (simd_immediate_info): Replace mvn
with an insn_type enum and msl with a modifier_type enum.
Replace element_width with a scalar_mode. Change the shift
to unsigned int. Add constructors for scalar_float_mode and
scalar_int_mode elements.
(aarch64_vect_float_const_representable_p): Delete.
(aarch64_can_const_movi_rtx_p)
(aarch64_simd_scalar_immediate_valid_for_move)
(aarch64_simd_make_constant): Update call to
aarch64_simd_valid_immediate.
(aarch64_advsimd_valid_immediate_hs): New function.
(aarch64_advsimd_valid_immediate): Likewise.
(aarch64_simd_valid_immediate): Remove mode and inverse
arguments. Rewrite to use the above. Use const_vec_duplicate_p
to detect duplicated constants and use aarch64_float_const_zero_rtx_p
and aarch64_float_const_representable_p on the result.
(aarch64_output_simd_mov_immediate): Remove mode argument.
Update call to aarch64_simd_valid_immediate and use of
simd_immediate_info.
(aarch64_output_scalar_simd_mov_immediate): Update call
accordingly.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* machmode.h (mode_precision): Prefix with CONST_MODE_PRECISION.
(mode_nunits): Likewise CONST_MODE_NUNITS.
* machmode.def (ADJUST_NUNITS): Document.
......
gcc/config/aarch64/aarch64-protos.h
......@@ -368,7 +368,7 @@ bool aarch64_mov_operand_p (rtx, machine_mode);
rtx aarch64_reverse_mask (machine_mode, unsigned int);
bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT);
char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned,
char *aarch64_output_simd_mov_immediate (rtx, unsigned,
enum simd_immediate_check w = AARCH64_CHECK_MOV);
bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);
bool aarch64_regno_ok_for_base_p (int, bool);
......@@ -379,8 +379,7 @@ bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode,
bool aarch64_simd_imm_zero_p (rtx, machine_mode);
bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode);
bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
bool aarch64_simd_valid_immediate (rtx, machine_mode, bool,
struct simd_immediate_info *,
bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
enum simd_immediate_check w = AARCH64_CHECK_MOV);
bool aarch64_split_dimode_const_store (rtx, rtx);
bool aarch64_symbolic_address_p (rtx);
......
gcc/config/aarch64/aarch64-simd.md
......@@ -120,8 +120,7 @@
case 5: return "fmov\t%d0, %1";
case 6: return "mov\t%0, %1";
case 7:
return aarch64_output_simd_mov_immediate (operands[1],
<MODE>mode, 64);
return aarch64_output_simd_mov_immediate (operands[1], 64);
default: gcc_unreachable ();
}
}
......@@ -154,7 +153,7 @@
case 6:
return "#";
case 7:
return aarch64_output_simd_mov_immediate (operands[1], <MODE>mode, 128);
return aarch64_output_simd_mov_immediate (operands[1], 128);
default:
gcc_unreachable ();
}
......@@ -647,8 +646,8 @@
case 0:
return "and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>";
case 1:
return aarch64_output_simd_mov_immediate (operands[2],
<MODE>mode, GET_MODE_BITSIZE (<MODE>mode), AARCH64_CHECK_BIC);
return aarch64_output_simd_mov_immediate (operands[2], <bitsize>,
AARCH64_CHECK_BIC);
default:
gcc_unreachable ();
}
......@@ -668,8 +667,8 @@
case 0:
return "orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>";
case 1:
return aarch64_output_simd_mov_immediate (operands[2],
<MODE>mode, GET_MODE_BITSIZE (<MODE>mode), AARCH64_CHECK_ORR);
return aarch64_output_simd_mov_immediate (operands[2], <bitsize>,
AARCH64_CHECK_ORR);
default:
gcc_unreachable ();
}
......
gcc/config/aarch64/constraints.md
......@@ -210,22 +210,21 @@
"@internal
A constraint that matches vector of immediates for orr."
(and (match_code "const_vector")
(match_test "aarch64_simd_valid_immediate (op, mode, false,
NULL, AARCH64_CHECK_ORR)")))
(match_test "aarch64_simd_valid_immediate (op, NULL,
AARCH64_CHECK_ORR)")))
(define_constraint "Db"
"@internal
A constraint that matches vector of immediates for bic."
(and (match_code "const_vector")
(match_test "aarch64_simd_valid_immediate (op, mode, false,
NULL, AARCH64_CHECK_BIC)")))
(match_test "aarch64_simd_valid_immediate (op, NULL,
AARCH64_CHECK_BIC)")))
(define_constraint "Dn"
"@internal
A constraint that matches vector of immediates."
(and (match_code "const_vector")
(match_test "aarch64_simd_valid_immediate (op, GET_MODE (op),
false, NULL)")))
(match_test "aarch64_simd_valid_immediate (op, NULL)")))
(define_constraint "Dh"
"@internal
......
gcc/config/aarch64/iterators.md
......@@ -461,6 +461,13 @@
(V1DF "1") (V2DF "2")
(DI "1") (DF "1")])
;; Map a mode to the number of bits in it, if the size of the mode
;; is constant.
(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
(V4HI "64") (V8HI "128")
(V2SI "64") (V4SI "128")
(V2DI "128")])
;; Map a floating point or integer mode to the appropriate register name prefix
(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
......
gcc/config/aarch64/predicates.md
......@@ -72,14 +72,14 @@
(define_predicate "aarch64_reg_or_orr_imm"
(ior (match_operand 0 "register_operand")
(and (match_code "const_vector")
(match_test "aarch64_simd_valid_immediate (op, mode, false,
NULL, AARCH64_CHECK_ORR)"))))
(match_test "aarch64_simd_valid_immediate (op, NULL,
AARCH64_CHECK_ORR)"))))
(define_predicate "aarch64_reg_or_bic_imm"
(ior (match_operand 0 "register_operand")
(and (match_code "const_vector")
(match_test "aarch64_simd_valid_immediate (op, mode, false,
NULL, AARCH64_CHECK_BIC)"))))
(match_test "aarch64_simd_valid_immediate (op, NULL,
AARCH64_CHECK_BIC)"))))
(define_predicate "aarch64_fp_compare_operand"
(ior (match_operand 0 "register_operand")
......
gcc/testsuite/ChangeLog
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* gcc.target/aarch64/vect-movi.c (movi_float_lsl24): New function.
(main): Call it.
2018-01-03 Jeff Law <law@redhat.com>
PR target/83641
......
gcc/testsuite/gcc.target/aarch64/vect-movi.c
......@@ -45,10 +45,21 @@ mvni_msl16 (int *__restrict a)
a[i] = 0xff540000;
}
static void
movi_float_lsl24 (float * a)
{
int i;
/* { dg-final { scan-assembler {\tmovi\tv[0-9]+\.[42]s, 0x43, lsl 24\n} } } */
for (i = 0; i < N; i++)
a[i] = 128.0;
}
int
main (void)
{
int a[N] = { 0 };
float b[N] = { 0 };
int i;
#define CHECK_ARRAY(a, val) \
......@@ -68,6 +79,9 @@ main (void)
mvni_msl16 (a);
CHECK_ARRAY (a, 0xff540000);
movi_float_lsl24 (b);
CHECK_ARRAY (b, 128.0);
return 0;
}
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