arm.c (arm_arch5e): New variable.

* arm.c (arm_arch5e): New variable.
(all_cores): XScale is a 5TE device.
(arm_override_options): Set arm_arch5e.
(arm_init_builtins): __builtin_prefetch is in arch5e.
* arm.h (arm_arch5e): Declare it.

* arm.h (PREDICATE_CODES): Add arm_hard_register_operand.

* arm.md (define_constants): Add defines for UNSPEC and
UNSPEC_VOLATILE insns.  Update all users.
(define_constants): Add constants for IP_REGNUM, SP_REGNUM, PC_REGNUM.
* arm.c (multi_register_push, note_invalid_constants)
(emit_multi_reg_push, emit_sfm, expand_prologue): Use constants.
* arm.h (SP_REGNUM, IP_REGNUM, PC_REGNUM): Delete defines.
(STACK_POINTER_REGNUM): Define in terms of SP_REGNUM.

From-SVN: r38803

gcc/ChangeLog

+2001-01-08  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.c (arm_arch5e): New variable.
+	(all_cores): XScale is a 5TE device.
+	(arm_override_options): Set arm_arch5e.
+	(arm_init_builtins): __builtin_prefetch is in arch5e.
+	* arm.h (arm_arch5e): Declare it.
+
+	* arm.h (PREDICATE_CODES): Add arm_hard_register_operand.
+
+	* arm.md (define_constants): Add defines for UNSPEC and
+	UNSPEC_VOLATILE insns.  Update all users.
+	(define_constants): Add constants for IP_REGNUM, SP_REGNUM, PC_REGNUM.
+	* arm.c (multi_register_push, note_invalid_constants)
+	(emit_multi_reg_push, emit_sfm, expand_prologue): Use constants.
+	* arm.h (SP_REGNUM, IP_REGNUM, PC_REGNUM): Delete defines.
+	(STACK_POINTER_REGNUM): Define in terms of SP_REGNUM.
+	
 Mon Jan  8 16:14:56 MET 2001  Jan Hubicka  <jh@suse.cz>
 
 	* jump.c (jump_optimize_1): Use reversed_comparison_code

gcc/config/arm/arm.c

@@ -151,7 +151,7 @@ int    arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
 #define FL_THUMB      (1 << 6)        /* Thumb aware */
 #define FL_LDSCHED    (1 << 7)	      /* Load scheduling necessary */
 #define FL_STRONG     (1 << 8)	      /* StrongARM */
-#define FL_ARCH5E     (1 << 9)        /* El Segundo extenstions to v5 */
+#define FL_ARCH5E     (1 << 9)        /* DSP extenstions to v5 */
 #define FL_XSCALE     (1 << 10)	      /* XScale */
 
 /* The bits in this mask specify which instructions we are
@@ -176,6 +176,9 @@ int arm_arch4 = 0;
 /* Nonzero if this chip supports the ARM Architecture 5 extensions.  */
 int arm_arch5 = 0;
 
+/* Nonzero if this chip supports the ARM Architecture 5E extensions.  */
+int arm_arch5e = 0;
+
 /* Nonzero if this chip can benefit from load scheduling.  */
 int arm_ld_sched = 0;
 
@@ -279,7 +282,7 @@ static struct processors all_cores[] =
   {"strongarm",	             FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 |            FL_LDSCHED | FL_STRONG },
   {"strongarm110",           FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 |            FL_LDSCHED | FL_STRONG },
   {"strongarm1100",          FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 |            FL_LDSCHED | FL_STRONG },
-  {"xscale",                             FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_ARCH5 },
+  {"xscale",                             FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_ARCH5 | FL_ARCH5E },
   
   {NULL, 0}
 };
@@ -586,6 +589,7 @@ arm_override_options ()
   arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
   arm_arch4         = (insn_flags & FL_ARCH4) != 0;
   arm_arch5         = (insn_flags & FL_ARCH5) != 0;
+  arm_arch5e        = (insn_flags & FL_ARCH5E) != 0;
   arm_is_xscale     = (insn_flags & FL_XSCALE) != 0;
 
   arm_ld_sched      = (tune_flags & FL_LDSCHED) != 0;
@@ -4054,7 +4058,7 @@ multi_register_push (op, mode)
   if (GET_CODE (op) != PARALLEL
       || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
       || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
-      || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
+      || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
     return 0;
 
   return 1;
@@ -5888,7 +5892,7 @@ note_invalid_constants (insn, address)
 	     this shouldn't be needed any more.  */
 #ifndef AOF_ASSEMBLER
 	  /* XXX Is this still needed?  */
-	  else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
+	  else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
 	    push_minipool_fix (insn, address, recog_data.operand_loc[opno],
 			       recog_data.operand_mode[opno],
 			       XVECEXP (op, 0, 0));
@@ -7593,7 +7597,8 @@ emit_multi_reg_push (mask)
      something like this:
 
        (parallel [ 
-           (set (mem:BLK (pre_dec:BLK (reg:SI sp))) (unspec:BLK [(reg:SI r4)] 2))
+           (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
+	        (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
            (use (reg:SI 11 fp))
            (use (reg:SI 12 ip))
            (use (reg:SI 14 lr))
@@ -7708,7 +7713,7 @@ emit_sfm (base_reg, count)
 				gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
 		   gen_rtx_UNSPEC (BLKmode,
 				   gen_rtvec (1, reg),
-				   2));
+				   UNSPEC_PUSH_MULT));
   tmp
     = gen_rtx_SET (VOIDmode, 
 		   gen_rtx_MEM (XFmode,
@@ -7941,7 +7946,8 @@ arm_expand_prologue ()
 	{
 	  rtx unspec = gen_rtx_UNSPEC (SImode,
 				       gen_rtvec (2, stack_pointer_rtx,
-						  hard_frame_pointer_rtx), 4);
+						  hard_frame_pointer_rtx),
+				       UNSPEC_PRLG_STK);
 
 	  insn = emit_insn (gen_rtx_CLOBBER (VOIDmode,
 				      gen_rtx_MEM (BLKmode, unspec)));
@@ -8801,6 +8807,11 @@ arm_init_builtins ()
   if (arm_arch5)
     {
       def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ);
+    }
+
+  /* Initialize arm V5E builtins.  */
+  if (arm_arch5e)
+    {
       def_builtin ("__builtin_prefetch", void_ftype_pchar,
 		   ARM_BUILTIN_PREFETCH);
     }

gcc/config/arm/arm.h

@@ -561,6 +561,9 @@ extern int arm_arch4;
 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
 extern int arm_arch5;
 
+/* Nonzero if this chip supports the ARM Architecture 5E extensions */
+extern int arm_arch5e;
+
 /* Nonzero if this chip can benefit from load scheduling.  */
 extern int arm_ld_sched;
 
@@ -931,32 +934,21 @@ extern const char * structure_size_string;
    pointer.  */
 #define ARM_HARD_FRAME_POINTER_REGNUM	11
 #define THUMB_HARD_FRAME_POINTER_REGNUM	 7
-#define HARD_FRAME_POINTER_REGNUM       (TARGET_ARM ? ARM_HARD_FRAME_POINTER_REGNUM : THUMB_HARD_FRAME_POINTER_REGNUM)
-#define FP_REGNUM	                HARD_FRAME_POINTER_REGNUM
-
-/* Scratch register - used in all kinds of places, eg trampolines.  */
-#define IP_REGNUM		12
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM	13
-#define SP_REGNUM	        STACK_POINTER_REGNUM
 
-/* Register which holds return address from a subroutine call.  */
-#define LR_REGNUM		14
+#define HARD_FRAME_POINTER_REGNUM		\
+  (TARGET_ARM					\
+   ? ARM_HARD_FRAME_POINTER_REGNUM		\
+   : THUMB_HARD_FRAME_POINTER_REGNUM)
 
-/* Define this if the program counter is overloaded on a register.  */
-#define PC_REGNUM		15
+#define FP_REGNUM	                HARD_FRAME_POINTER_REGNUM
 
-/* The number of the last ARM (integer) register.  */
-#define LAST_ARM_REGNUM 	15
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM	SP_REGNUM
 
 /* ARM floating pointer registers.  */
 #define FIRST_ARM_FP_REGNUM 	16
 #define LAST_ARM_FP_REGNUM  	23
 
-/* Internal, so that we don't need to refer to a raw number */
-#define CC_REGNUM		24
-
 /* Base register for access to local variables of the function.  */
 #define FRAME_POINTER_REGNUM	25
 
@@ -2949,6 +2941,7 @@ extern int making_const_table;
 /* Define the codes that are matched by predicates in arm.c */
 #define PREDICATE_CODES							\
   {"s_register_operand", {SUBREG, REG}},				\
+  {"arm_hard_register_operand", {REG}},					\
   {"f_register_operand", {SUBREG, REG}},				\
   {"arm_add_operand",    {SUBREG, REG, CONST_INT}},			\
   {"fpu_add_operand",    {SUBREG, REG, CONST_DOUBLE}},			\