[PATCH, rs6000, testsuite] Fix PR87306

    PR target/87306
    * gcc.dg/vect/bb-slp-pow-1.c: Modify to reflect that
    the loop is not vectorized on POWER unless hardware 
    misaligned loads are available.

From-SVN: r268003

gcc/testsuite/ChangeLog

+2019-01-17  Kewen Lin  <linkw@gcc.gnu.org>
+
+	PR target/87306
+	* gcc.dg/vect/bb-slp-pow-1.c: Modify to reflect that the loop is not
+	vectorized on POWER unless hardware misaligned loads are available.
+
 2019-01-16  David Malcolm  <dmalcolm@redhat.com>
 
 	PR target/88861

gcc/testsuite/gcc.dg/vect/bb-slp-pow-1.c

@@ -25,4 +25,8 @@ main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" } } */
+/* On older powerpc hardware (POWER7 and earlier), the default flag
+   -mno-allow-movmisalign prevents vectorization.  On POWER8 and later,
+   when vect_hw_misalign is true, vectorization occurs.  */
+
+/* { dg-final { scan-tree-dump-times "basic block vectorized" 1 "slp2" { target {{ ! powerpc*-*-* } || { powerpc*-*-* && vect_hw_misalign }} } } } */