i386.h (FIRST_PSEUDO_REGISTER): Define to 53.

	* config/i386/i386.h (FIRST_PSEUDO_REGISTER): Define to 53.
	(FIXED_REGISTERS, CALL_USED_REGISTERS): Remove dir register.
	(REG_ALLOC_ORDER): Remove one element due to removal of dir register.
	(FRAME_POINTER_REGNUM): Update register number to 20.
	(REG_CLASS_CONTENTS): Update contents due to removed dir register.
	(HI_REGISTER_NAMES): Remove "dirflag".

	* config/i386/i386.c (regclass_map): Remove dirflag entry.
	(dbx_register_map, dbx64_register_map, svr4_dbx_register_map):
	Remove "dir" entry.
	(ix86_md_asm_clobbers): Remove "dirflag" default asm clobber.

	* config/i386/i386.md (R10_REG, R11_REG): Renumber.
	(sse_prologue_save, *sse_prologue_save_insn): Renumber
	hardcoded SSE register numbers.

	* config/i386/mmx.md (mmx_emms, mmx_femms): Renumber
	hardcoded MMX register numbers.

From-SVN: r119839

gcc/ChangeLog

+2006-12-13  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.h (FIRST_PSEUDO_REGISTER): Define to 53.
+	(FIXED_REGISTERS, CALL_USED_REGISTERS): Remove dir register.
+	(REG_ALLOC_ORDER): Remove one element due to removal of dir register.
+	(FRAME_POINTER_REGNUM): Update register number to 20.
+	(REG_CLASS_CONTENTS): Update contents due to removed dir register.
+	(HI_REGISTER_NAMES): Remove "dirflag".
+
+	* config/i386/i386.c (regclass_map): Remove dirflag entry.
+	(dbx_register_map, dbx64_register_map, svr4_dbx_register_map):
+	Remove "dir" entry.
+	(ix86_md_asm_clobbers): Remove "dirflag" default asm clobber.
+
+	* config/i386/i386.md (R10_REG, R11_REG): Renumber.
+	(sse_prologue_save, *sse_prologue_save_insn): Renumber
+	hardcoded SSE register numbers.
+
+	* config/i386/mmx.md (mmx_emms, mmx_femms): Renumber
+	hardcoded MMX register numbers.
+
+
 2006-12-13  Mark Shinwell  <shinwell@codesourcery.com>
 
 	* config/arm/arm.c (arm_output_fldmx): Output FLDMD instead of

gcc/config/i386/i386.c

@@ -1052,8 +1052,8 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
   FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
   /* arg pointer */
   NON_Q_REGS,
-  /* flags, fpsr, fpcr, dirflag, frame */
-  NO_REGS, NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
+  /* flags, fpsr, fpcr, frame */
+  NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
   SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
   SSE_REGS, SSE_REGS,
   MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
@@ -1070,7 +1070,7 @@ int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 2, 1, 3, 6, 7, 4, 5,		/* general regs */
   12, 13, 14, 15, 16, 17, 18, 19,	/* fp regs */
-  -1, -1, -1, -1, -1, -1,		/* arg, flags, fpsr, fpcr, dir, frame */
+  -1, -1, -1, -1, -1,			/* arg, flags, fpsr, fpcr, frame */
   21, 22, 23, 24, 25, 26, 27, 28,	/* SSE */
   29, 30, 31, 32, 33, 34, 35, 36,       /* MMX */
   -1, -1, -1, -1, -1, -1, -1, -1,	/* extended integer registers */
@@ -1093,7 +1093,7 @@ int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 1, 2, 3, 4, 5, 6, 7,		/* general regs */
   33, 34, 35, 36, 37, 38, 39, 40,	/* fp regs */
-  -1, -1, -1, -1, -1, -1,		/* arg, flags, fpsr, fpcr, dir, frame */
+  -1, -1, -1, -1, -1,			/* arg, flags, fpsr, fpcr, frame */
   17, 18, 19, 20, 21, 22, 23, 24,	/* SSE */
   41, 42, 43, 44, 45, 46, 47, 48,       /* MMX */
   8,9,10,11,12,13,14,15,		/* extended integer registers */
@@ -1158,7 +1158,7 @@ int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 2, 1, 3, 6, 7, 5, 4,		/* general regs */
   11, 12, 13, 14, 15, 16, 17, 18,	/* fp regs */
-  -1, 9, -1, -1, -1, -1,		/* arg, flags, fpsr, fpcr, dir, frame */
+  -1, 9, -1, -1, -1,			/* arg, flags, fpsr, fpcr, frame */
   21, 22, 23, 24, 25, 26, 27, 28,	/* SSE registers */
   29, 30, 31, 32, 33, 34, 35, 36,	/* MMX registers */
   -1, -1, -1, -1, -1, -1, -1, -1,	/* extended integer registers */
@@ -19927,8 +19927,6 @@ ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
 			clobbers);
   clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
 			clobbers);
-  clobbers = tree_cons (NULL_TREE, build_string (7, "dirflag"),
-			clobbers);
   return clobbers;
 }
 

gcc/config/i386/i386.h

@@ -768,7 +768,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
    eliminated during reloading in favor of either the stack or frame
    pointer.  */
 
-#define FIRST_PSEUDO_REGISTER 54
+#define FIRST_PSEUDO_REGISTER 53
 
 /* Number of hardware registers that go into the DWARF-2 unwind info.
    If not defined, equals FIRST_PSEUDO_REGISTER.  */
@@ -788,8 +788,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 #define FIXED_REGISTERS						\
 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/	\
 {  0, 0, 0, 0, 0, 0, 0, 1, 0,  0,  0,  0,  0,  0,  0,  0,	\
-/*arg,flags,fpsr,fpcr,dir,frame*/				\
-    1,    1,   1,   1,  1,    1,				\
+/*arg,flags,fpsr,fpcr,frame*/					\
+    1,    1,   1,   1,    1,					\
 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/			\
      0,   0,   0,   0,   0,   0,   0,   0,			\
 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/			\
@@ -816,8 +816,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 #define CALL_USED_REGISTERS					\
 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/	\
 {  1, 1, 1, 0, 3, 3, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,	\
-/*arg,flags,fpsr,fpcr,dir,frame*/				\
-    1,   1,    1,   1,  1,    1,				\
+/*arg,flags,fpsr,fpcr,frame*/					\
+    1,   1,    1,   1,    1,					\
 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/			\
      1,   1,   1,   1,   1,   1,   1,   1,			\
 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/			\
@@ -840,7 +840,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 {  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
    18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,	\
    33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,  \
-   48, 49, 50, 51, 52, 53 }
+   48, 49, 50, 51, 52 }
 
 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
    to be rearranged based on a particular function.  When using sse math,
@@ -1006,7 +1006,7 @@ do {									\
 #define HARD_FRAME_POINTER_REGNUM 6
 
 /* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 21
+#define FRAME_POINTER_REGNUM 20
 
 /* First floating point reg */
 #define FIRST_FLOAT_REG 8
@@ -1200,21 +1200,21 @@ enum reg_class
       { 0x10,     0x0 }, { 0x20, 0x0 },	/* SIREG, DIREG */		\
       { 0x03,     0x0 },		/* AD_REGS */			\
       { 0x0f,     0x0 },		/* Q_REGS */			\
-  { 0x2100f0,  0x3fc0 },		/* NON_Q_REGS */		\
-      { 0x7f,  0x3fc0 },		/* INDEX_REGS */		\
-  { 0x2100ff,     0x0 },		/* LEGACY_REGS */		\
-  { 0x2100ff,  0x3fc0 },		/* GENERAL_REGS */		\
+  { 0x1100f0,  0x1fe0 },		/* NON_Q_REGS */		\
+      { 0x7f,  0x1fe0 },		/* INDEX_REGS */		\
+  { 0x1100ff,     0x0 },		/* LEGACY_REGS */		\
+  { 0x1100ff,  0x1fe0 },		/* GENERAL_REGS */		\
      { 0x100,     0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
     { 0xff00,     0x0 },		/* FLOAT_REGS */		\
-{ 0x3fc00000,0x3fc000 },		/* SSE_REGS */			\
-{ 0xc0000000,    0x3f },		/* MMX_REGS */			\
-{ 0x3fc00100,0x3fc000 },		/* FP_TOP_SSE_REG */		\
-{ 0x3fc00200,0x3fc000 },		/* FP_SECOND_SSE_REG */		\
-{ 0x3fc0ff00,0x3fc000 },		/* FLOAT_SSE_REGS */		\
-   { 0x1ffff,  0x3fc0 },		/* FLOAT_INT_REGS */		\
-{ 0x3fc100ff,0x3fffc0 },		/* INT_SSE_REGS */		\
-{ 0x3fc1ffff,0x3fffc0 },		/* FLOAT_INT_SSE_REGS */	\
-{ 0xffffffff,0x3fffff }							\
+{ 0x1fe00000,0x1fe000 },		/* SSE_REGS */			\
+{ 0xe0000000,    0x1f },		/* MMX_REGS */			\
+{ 0x1fe00100,0x1fe000 },		/* FP_TOP_SSE_REG */		\
+{ 0x1fe00200,0x1fe000 },		/* FP_SECOND_SSE_REG */		\
+{ 0x1fe0ff00,0x3fe000 },		/* FLOAT_SSE_REGS */		\
+   { 0x1ffff,  0x1fe0 },		/* FLOAT_INT_REGS */		\
+{ 0x1fe100ff,0x1fffe0 },		/* INT_SSE_REGS */		\
+{ 0x1fe1ffff,0x1fffe0 },		/* FLOAT_INT_SSE_REGS */	\
+{ 0xffffffff,0x1fffff }							\
 }
 
 /* The same information, inverted:
@@ -1953,7 +1953,7 @@ do {							\
 #define HI_REGISTER_NAMES						\
 {"ax","dx","cx","bx","si","di","bp","sp",				\
  "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)",		\
- "argp", "flags", "fpsr", "fpcr", "dirflag", "frame",			\
+ "argp", "flags", "fpsr", "fpcr", "frame",				\
  "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7",		\
  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",		\
  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",			\

gcc/config/i386/i386.md

@@ -180,8 +180,8 @@
    (FLAGS_REG			17)
    (FPSR_REG			18)
    (FPCR_REG			19)
-   (R10_REG			40)
-   (R11_REG			41)
+   (R10_REG			39)
+   (R11_REG			40)
   ])
 
 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
@@ -20765,14 +20765,14 @@
 
 (define_expand "sse_prologue_save"
   [(parallel [(set (match_operand:BLK 0 "" "")
-		   (unspec:BLK [(reg:DI 22)
+		   (unspec:BLK [(reg:DI 21)
+				(reg:DI 22)
 				(reg:DI 23)
 				(reg:DI 24)
 				(reg:DI 25)
 				(reg:DI 26)
 				(reg:DI 27)
-				(reg:DI 28)
-				(reg:DI 29)] UNSPEC_SSE_PROLOGUE_SAVE))
+				(reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
 	      (use (match_operand:DI 1 "register_operand" ""))
 	      (use (match_operand:DI 2 "immediate_operand" ""))
 	      (use (label_ref:DI (match_operand 3 "" "")))])]
@@ -20782,14 +20782,14 @@
 (define_insn "*sse_prologue_save_insn"
   [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
 			  (match_operand:DI 4 "const_int_operand" "n")))
-	(unspec:BLK [(reg:DI 22)
+	(unspec:BLK [(reg:DI 21)
+		     (reg:DI 22)
 		     (reg:DI 23)
 		     (reg:DI 24)
 		     (reg:DI 25)
 		     (reg:DI 26)
 		     (reg:DI 27)
-		     (reg:DI 28)
-		     (reg:DI 29)] UNSPEC_SSE_PROLOGUE_SAVE))
+		     (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
    (use (match_operand:DI 1 "register_operand" "r"))
    (use (match_operand:DI 2 "const_int_operand" "i"))
    (use (label_ref:DI (match_operand 3 "" "X")))]

gcc/config/i386/mmx.md

@@ -1396,14 +1396,14 @@
    (clobber (reg:XF 13))
    (clobber (reg:XF 14))
    (clobber (reg:XF 15))
+   (clobber (reg:DI 29))
    (clobber (reg:DI 30))
    (clobber (reg:DI 31))
    (clobber (reg:DI 32))
    (clobber (reg:DI 33))
    (clobber (reg:DI 34))
    (clobber (reg:DI 35))
-   (clobber (reg:DI 36))
-   (clobber (reg:DI 37))]
+   (clobber (reg:DI 36))]
   "TARGET_MMX"
   "emms"
   [(set_attr "type" "mmx")
@@ -1419,14 +1419,14 @@
    (clobber (reg:XF 13))
    (clobber (reg:XF 14))
    (clobber (reg:XF 15))
+   (clobber (reg:DI 29))
    (clobber (reg:DI 30))
    (clobber (reg:DI 31))
    (clobber (reg:DI 32))
    (clobber (reg:DI 33))
    (clobber (reg:DI 34))
    (clobber (reg:DI 35))
-   (clobber (reg:DI 36))
-   (clobber (reg:DI 37))]
+   (clobber (reg:DI 36))]
   "TARGET_3DNOW"
   "femms"
   [(set_attr "type" "mmx")