alpha.md (extxl+1,+2): New patterns to work around combine lossage.

        * alpha.md (extxl+1,+2): New patterns to work around
        combine lossage.

From-SVN: r21651

gcc/ChangeLog

+Mon Aug 10 01:21:01 1998  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.md (extxl+1,+2): New patterns to work around
+	combine lossage.
+
 Sat Aug  8 19:20:22 1998 Gary Thomas (gdt@linuxppc.org)
 
 	* rs6000.c (rs6000_allocate_stack_space) Fix typo which

gcc/config/alpha/alpha.md

@@ -1495,6 +1495,29 @@
   "ext%M2l %r1,%3,%0"
   [(set_attr "type" "shift")])
 
+;; Combine has some strange notion of preserving existing undefined behaviour
+;; in shifts larger than a word size.  So capture these patterns that it 
+;; should have turned into zero_extracts.
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(and (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+		(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
+			   (const_int 3)))
+	     (match_operand:DI 3 "mode_mask_operand" "n")))]
+  ""
+  "ext%U3l %1,%2,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+	  (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
+		     (const_int 3))))]
+  ""
+  "extql %1,%2,%0"
+  [(set_attr "type" "shift")])
+
 (define_insn "extqh"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI