Skip to content

R
riscv-gcc-1
Commit b03149e1 by Jie Zhang Committed by Jie Zhang
Options

bfin-protos.h (bfin_hardware_loop): Declare. 

	* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
	* config/bfin/bfin.c (basic-block.h): Include.
	(struct machine_function): New.
	(bfin_init_machine_status): New.
	(override_options): Initialize init_machine_status.
	(bfin_hardware_loop): New.
	(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
	(DEF_VEC_P (loop_info)): New.
	(DEF_VEC_ALLOC_P (loop_info,heap)): New.
	(struct loop_info): New.
	(loop_info): New typedef.
	(struct loop_work): New.
	(loop_work): New typedef.
	(DEF_VEC_O (loop_work)): New.
	(DEF_VEC_ALLOC_O (loop_work,heap)): New.
	(bfin_dump_loops): New.
	(bfin_bb_in_loop): New.
	(bfin_scan_loop): New.
	(bfin_optimize_loop): New.
	(bfin_reorg_loops): New.
	(bfin_reorg): Use bfin_reorg_loops.
	* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
	loop registers.
	(I_REGNO_P): Simplify.
	(DP_REGNO_P, DPREG_P): New macros.
	(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
	REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
	(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
	Add LT_REGS, LC_REGS, LB_REGS.
	(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
	'l' for LB_REGS.
	(REGNO_REG_CLASS): Deal with loop registers.
	* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
	letters.
	(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
	New constants for loop registers.
	(UNSPEC_LSETUP_END): New.
	(seq_insns): New define_attr. Set it for appropriate insns.
	(movsi_insn): Add alternatives for move from/to
	loop count registers.
	(doloop_end): New define_expand.
	(loop_end): New define_insn.
	(define_split for bad doloop_end): New.
	(lsetup_with_autoinit): New define_insn.
	(lsetup_without_autoinit): New define_insn.
	(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
	* config/bfin/predicates.md (lc_register_operand): New.
	(lt_register_operand): New.
	(lb_register_operand): New.
	(nondp_register_operand): New.
	(nondp_reg_or_memory_operand): New.
        * doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.

From-SVN: r114274
parent 5dd59f65
Showing with 126 additions and 15 deletions
gcc/ChangeLog
2006-05-31 Jie Zhang <jie.zhang@analog.com>
* config/bfin/bfin-protos.h (bfin_hardware_loop): Declare.
* config/bfin/bfin.c (basic-block.h): Include.
(struct machine_function): New.
(bfin_init_machine_status): New.
(override_options): Initialize init_machine_status.
(bfin_hardware_loop): New.
(MAX_LOOP_DEPTH, MAX_LOOP_LENGTH): Define.
(DEF_VEC_P (loop_info)): New.
(DEF_VEC_ALLOC_P (loop_info,heap)): New.
(struct loop_info): New.
(loop_info): New typedef.
(struct loop_work): New.
(loop_work): New typedef.
(DEF_VEC_O (loop_work)): New.
(DEF_VEC_ALLOC_O (loop_work,heap)): New.
(bfin_dump_loops): New.
(bfin_bb_in_loop): New.
(bfin_scan_loop): New.
(bfin_optimize_loop): New.
(bfin_reorg_loops): New.
(bfin_reorg): Use bfin_reorg_loops.
* config/bfin/bfin.h (FIRST_PSEUDO_REGISTER): Adjust for adding
loop registers.
(I_REGNO_P): Simplify.
(DP_REGNO_P, DPREG_P): New macros.
(REGISTER_NAMES, FIXED_REGISTERS, CALL_USED_REGISTERS,
REG_ALLOC_ORDER): Add LT0, LT1, LC0, LC1, LB0, LB1.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
Add LT_REGS, LC_REGS, LB_REGS.
(REG_CLASS_FROM_LETTER): Add 't' for LT_REGS, 'k' for LC_REGS,
'l' for LB_REGS.
(REGNO_REG_CLASS): Deal with loop registers.
* config/bfin/bfin.md: Add comment for 't', 'k', 'l' constraint
letters.
(REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1):
New constants for loop registers.
(UNSPEC_LSETUP_END): New.
(seq_insns): New define_attr. Set it for appropriate insns.
(movsi_insn): Add alternatives for move from/to
loop count registers.
(doloop_end): New define_expand.
(loop_end): New define_insn.
(define_split for bad doloop_end): New.
(lsetup_with_autoinit): New define_insn.
(lsetup_without_autoinit): New define_insn.
(rep_movsi, rep_movhi): Clobber LT1, LC1, LB1.
* config/bfin/predicates.md (lc_register_operand): New.
(lt_register_operand): New.
(lb_register_operand): New.
(nondp_register_operand): New.
(nondp_reg_or_memory_operand): New.
* doc/md.texi: Document Blackfin new 't', 'k', 'l' constraint letters.
2006-05-31 Jie Zhang <jie.zhang@analog.com>
* config/bfin/bfin.c (bfin_delegitimize_address): New.
(TARGET_DELEGITIMIZE_ADDRESS): Define.
......
gcc/config/bfin/bfin-protos.h
......@@ -83,6 +83,7 @@ extern void output_push_multiple (rtx, rtx *);
extern void output_pop_multiple (rtx, rtx *);
extern int bfin_hard_regno_rename_ok (unsigned int, unsigned int);
extern rtx bfin_return_addr_rtx (int);
extern void bfin_hardware_loop (void);
#undef Mmode
#endif
......
gcc/config/bfin/bfin.h
......@@ -268,15 +268,17 @@ extern const char *bfin_library_id_string;
5 return address registers RETS/I/X/N/E
1 arithmetic status register (ASTAT). */
#define FIRST_PSEUDO_REGISTER 44
#define FIRST_PSEUDO_REGISTER 50
#define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
#define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
#define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
#define D_REGNO_P(X) ((X) <= REG_R7)
#define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
#define I_REGNO_P(X) \
((X) == REG_I0 || (X) == REG_I1 || (X) == REG_I2 || (X) == REG_I3)
#define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
#define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
#define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
#define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
#define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
#define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
#define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
#define REGISTER_NAMES { \
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
......@@ -286,7 +288,8 @@ extern const char *bfin_library_id_string;
"A0", "A1", \
"CC", \
"RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
"ARGP" \
"ARGP", \
"LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
}
#define SHORT_REGISTER_NAMES { \
......@@ -316,8 +319,10 @@ extern const char *bfin_library_id_string;
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
/*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \
0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/*lb0/1 */ \
1, 1 \
}
/* 1 for registers not available across function calls.
......@@ -332,8 +337,10 @@ extern const char *bfin_library_id_string;
{ 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
/*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/*lb0/1 */ \
1, 1 \
}
/* Order in which to allocate registers. Each register must be
......@@ -350,7 +357,8 @@ extern const char *bfin_library_id_string;
REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
REG_ASTAT, REG_SEQSTAT, REG_USP, \
REG_CC, REG_ARGP \
REG_CC, REG_ARGP, \
REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
}
/* Macro to conditionally modify fixed_regs/call_used_regs. */
......@@ -410,6 +418,9 @@ enum reg_class
IPREGS,
DPREGS,
MOST_REGS,
LT_REGS,
LC_REGS,
LB_REGS,
PROLOGUE_REGS,
NON_A_CC_REGS,
ALL_REGS, LIM_REG_CLASSES
......@@ -443,6 +454,9 @@ enum reg_class
"IPREGS", \
"DPREGS", \
"MOST_REGS", \
"LT_REGS", \
"LC_REGS", \
"LB_REGS", \
"PROLOGUE_REGS", \
"NON_A_CC_REGS", \
"ALL_REGS" }
......@@ -484,9 +498,12 @@ enum reg_class
{ 0x000fff00, 0x800 }, /* IPREGS */ \
{ 0x0000ffff, 0x800 }, /* DPREGS */ \
{ 0xffffffff, 0x800 }, /* MOST_REGS */\
{ 0x00000000, 0x7f8 }, /* PROLOGUE_REGS */\
{ 0xffffffff, 0xff8 }, /* NON_A_CC_REGS */\
{ 0xffffffff, 0xfff }} /* ALL_REGS */
{ 0x00000000, 0x3000 }, /* LT_REGS */\
{ 0x00000000, 0xc000 }, /* LC_REGS */\
{ 0x00000000, 0x30000 }, /* LB_REGS */\
{ 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
{ 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
{ 0xffffffff, 0x3ffff }} /* ALL_REGS */
#define IREG_POSSIBLE_P(OUTER) \
((OUTER) == POST_INC || (OUTER) == PRE_INC \
......@@ -535,6 +552,9 @@ enum reg_class
(LETTER) == 'f' ? MREGS : \
(LETTER) == 'c' ? CIRCREGS : \
(LETTER) == 'C' ? CCREGS : \
(LETTER) == 't' ? LT_REGS : \
(LETTER) == 'k' ? LC_REGS : \
(LETTER) == 'l' ? LB_REGS : \
(LETTER) == 'x' ? MOST_REGS : \
(LETTER) == 'y' ? PROLOGUE_REGS : \
(LETTER) == 'w' ? NON_A_CC_REGS : \
......@@ -554,6 +574,9 @@ enum reg_class
: (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
: (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
: (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
: (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
: (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
: (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
: (REGNO) == REG_CC ? CCREGS \
: (REGNO) >= REG_RETS ? PROLOGUE_REGS \
: NO_REGS)
......
gcc/config/bfin/predicates.md
......@@ -76,12 +76,44 @@
return 1;
})
;; Return nonzero if OP is a LC register.
(define_predicate "lc_register_operand"
(and (match_code "reg")
(match_test "REGNO (op) == REG_LC0 || REGNO (op) == REG_LC1")))
;; Return nonzero if OP is a LT register.
(define_predicate "lt_register_operand"
(and (match_code "reg")
(match_test "REGNO (op) == REG_LT0 || REGNO (op) == REG_LT1")))
;; Return nonzero if OP is a LB register.
(define_predicate "lb_register_operand"
(and (match_code "reg")
(match_test "REGNO (op) == REG_LB0 || REGNO (op) == REG_LB1")))
;; Return nonzero if OP is a register or a 7 bit signed constant.
(define_predicate "reg_or_7bit_operand"
(ior (match_operand 0 "register_operand")
(and (match_code "const_int")
(match_test "CONST_7BIT_IMM_P (INTVAL (op))"))))
;; Return nonzero if OP is a register other than DREG and PREG.
(define_predicate "nondp_register_operand"
(match_operand 0 "register_operand")
{
unsigned int regno;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
regno = REGNO (op);
return (regno >= FIRST_PSEUDO_REGISTER || !DP_REGNO_P (regno));
})
;; Return nonzero if OP is a register other than DREG and PREG, or MEM.
(define_predicate "nondp_reg_or_memory_operand"
(ior (match_operand 0 "nondp_register_operand")
(match_operand 0 "memory_operand")))
;; Used for secondary reloads, this function returns 1 if OP is of the
;; form (plus (fp) (const_int)).
(define_predicate "fp_plus_const_operand"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment