i386-cadd.c: Compile using -march=k8.

	* gcc.dg/i386-cadd.c:  Compile using -march=k8.
	* gcc.dg/i386-cmov?.c:  Likewise.
	* gcc.dg/i386-fpcvt-?.c:  Likewise.
	* gcc.dg/i386-ssefp-1.c:  Likewise.
	* gcc.dg/i386-ssetype-?.c:  Likewise; fix for register passing
	convetions.

From-SVN: r62394

gcc/testsuite/ChangeLog

+Tue Feb  4 21:41:09 CET 2003  Jan Hubicka  <jh@suse.cz>
+
+	* gcc.dg/i386-cadd.c:  Compile using -march=k8.
+	* gcc.dg/i386-cmov?.c:  Likewise.
+	* gcc.dg/i386-fpcvt-?.c:  Likewise.
+	* gcc.dg/i386-ssefp-1.c:  Likewise.
+	* gcc.dg/i386-ssetype-?.c:  Likewise; fix for register passing
+	convetions.
+
 2003-02-03  Mark Mitchell  <mark@codesourcery.com>
 
 	PR c++/7129

gcc/testsuite/gcc.dg/i386-cadd.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "sbb" } } */
 
 /* Conditional increment is best done using sbb $-1, val.  */

gcc/testsuite/gcc.dg/i386-cmov1.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "sar.*magic_namea" } } */
 /* { dg-final { scan-assembler "sar.*magic_nameb" } } */
 /* { dg-final { scan-assembler "sar.*magic_namec" } } */

gcc/testsuite/gcc.dg/i386-cmov2.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "sbb" } } */
 
 /* This conditional move is fastest to be done using sbb.  */

gcc/testsuite/gcc.dg/i386-cmov3.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "cmov" } } */
 
 /* This conditional move is fastest to be done using cmov.  */

gcc/testsuite/gcc.dg/i386-cmov4.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "cmov" } } */
 
 /* Verify that if conversion happends for memory references.  */

gcc/testsuite/gcc.dg/i386-cmov5.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "sbb" } } */
 
 int

gcc/testsuite/gcc.dg/i386-fpcvt-1.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler-not "cvtss2sd" } } */
 float a,b;
 main()

gcc/testsuite/gcc.dg/i386-fpcvt-2.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler-not "cvtss2sd" } } */
 float a,b;
 main()

gcc/testsuite/gcc.dg/i386-fpcvt-3.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler-not "cvtss2sd" } } */
 float a,b;
 main()

gcc/testsuite/gcc.dg/i386-mmx-3.c

 /* PR target/8870 */
 /* Originator: otaylor@redhat.com */
-/* { dg-do compile { target i?86-*-* } } */
-/* { dg-options "-O1 -mmmx -march=i686" } */
+/* { dg-do compile { target i?86-*-* x86_64-*-*} } */
+/* { dg-options "-O1 -mmmx -march=k8" } */
 
 typedef int v4hi __attribute__ ((mode (V4HI)));
 

gcc/testsuite/gcc.dg/i386-ssefp-1.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon -mfpmath=sse" } */
+/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */
 /* { dg-final { scan-assembler "maxsd" } } */
 /* { dg-final { scan-assembler "minsd" } } */
 double x;

gcc/testsuite/gcc.dg/i386-ssefp-2.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon -mfpmath=sse" } */
+/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */
 /* { dg-final { scan-assembler "maxsd" } } */
 /* { dg-final { scan-assembler "minsd" } } */
 double x;

gcc/testsuite/gcc.dg/i386-ssetype-1.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
-/* { dg-final { scan-assembler "andpd.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "andnpd.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "xorpd.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "orpd.*\[bs\]p" } } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andpd.*magic" } } */
+/* { dg-final { scan-assembler "andnpd.*magic" } } */
+/* { dg-final { scan-assembler "xorpd.*magic" } } */
+/* { dg-final { scan-assembler "orpd.*magic" } } */
 /* { dg-final { scan-assembler-not "movdqa" } } */
-/* { dg-final { scan-assembler "movapd.*\[bs\]p" } } */
+/* { dg-final { scan-assembler "movapd.*magic" } } */
 
 /* Verify that we generate proper instruction with memory operand.  */
 
 #include <xmmintrin.h>
+
+__m128d magic_a, magic_b;
+
 __m128d
-t1(__m128d a, __m128d b)
+t1(void)
 {
-return _mm_and_pd (a,b);
+return _mm_and_pd (magic_a,magic_b);
 }
 __m128d
-t2(__m128d a, __m128d b)
+t2(void)
 {
-return _mm_andnot_pd (a,b);
+return _mm_andnot_pd (magic_a,magic_b);
 }
 __m128d
-t3(__m128d a, __m128d b)
+t3(void)
 {
-return _mm_or_pd (a,b);
+return _mm_or_pd (magic_a,magic_b);
 }
 __m128d
-t4(__m128d a, __m128d b)
+t4(void)
 {
-return _mm_xor_pd (a,b);
+return _mm_xor_pd (magic_a,magic_b);
 }

gcc/testsuite/gcc.dg/i386-ssetype-2.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler "andpd" } } */
 /* { dg-final { scan-assembler "andnpd" } } */
 /* { dg-final { scan-assembler "xorpd" } } */

gcc/testsuite/gcc.dg/i386-ssetype-3.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
-/* { dg-final { scan-assembler "andps.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "andnps.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "xorps.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "orps.*\[bs\]p" } } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andps.*magic" } } */
+/* { dg-final { scan-assembler "andnps.*magic" } } */
+/* { dg-final { scan-assembler "xorps.*magic" } } */
+/* { dg-final { scan-assembler "orps.*magic" } } */
 /* { dg-final { scan-assembler-not "movdqa" } } */
-/* { dg-final { scan-assembler "movaps.*\[bs\]p" } } */
+/* { dg-final { scan-assembler "movaps.*magic" } } */
 
 /* Verify that we generate proper instruction with memory operand.  */
 
 #include <xmmintrin.h>
+
+__m128 magic_a, magic_b;
 __m128
-t1(__m128 a, __m128 b)
+t1(void)
 {
-return _mm_and_ps (a,b);
+return _mm_and_ps (magic_a,magic_b);
 }
 __m128
-t2(__m128 a, __m128 b)
+t2(void)
 {
-return _mm_andnot_ps (a,b);
+return _mm_andnot_ps (magic_a,magic_b);
 }
 __m128
-t3(__m128 a, __m128 b)
+t3(void)
 {
-return _mm_or_ps (a,b);
+return _mm_or_ps (magic_a,magic_b);
 }
 __m128
-t4(__m128 a, __m128 b)
+t4(void)
 {
-return _mm_xor_ps (a,b);
+return _mm_xor_ps (magic_a,magic_b);
 }

gcc/testsuite/gcc.dg/i386-ssetype-4.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler "andps" } } */
 /* { dg-final { scan-assembler "andnps" } } */
 /* { dg-final { scan-assembler "xorps" } } */

gcc/testsuite/gcc.dg/i386-ssetype-5.c

 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
-/* { dg-final { scan-assembler "pand.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "pandn.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "pxor.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "por.*\[bs\]p" } } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "pand.*magic" } } */
+/* { dg-final { scan-assembler "pandn.*magic" } } */
+/* { dg-final { scan-assembler "pxor.*magic" } } */
+/* { dg-final { scan-assembler "por.*magic" } } */
 /* { dg-final { scan-assembler "movdqa" } } */
-/* { dg-final { scan-assembler-not "movaps.*\[bs\]p" } } */
+/* { dg-final { scan-assembler-not "movaps.*magic" } } */
 
 /* Verify that we generate proper instruction with memory operand.  */
 
 #include <xmmintrin.h>
+__m128i magic_a, magic_b;
 __m128i
-t1(__m128i a, __m128i b)
+t1(void)
 {
-return _mm_and_si128 (a,b);
+return _mm_and_si128 (magic_a,magic_b);
 }
 __m128i
-t2(__m128i a, __m128i b)
+t2(void)
 {
-return _mm_andnot_si128 (a,b);
+return _mm_andnot_si128 (magic_a,magic_b);
 }
 __m128i
-t3(__m128i a, __m128i b)
+t3(void)
 {
-return _mm_or_si128 (a,b);
+return _mm_or_si128 (magic_a,magic_b);
 }
 __m128i
-t4(__m128i a, __m128i b)
+t4(void)
 {
-return _mm_xor_si128 (a,b);
+return _mm_xor_si128 (magic_a,magic_b);
 }