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riscv-gcc-1
Commit aff48e32 by Joern Rennecke
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(dect): Rewrite pattern so that it can be combined. 

From-SVN: r13307
parent 5c8c0abd
Showing with 3 additions and 14 deletions
gcc/config/sh/sh.md
...@@ -222,10 +222,6 @@ ...@@ -222,10 +222,6 @@
"" ""
"movt %0") "movt %0")
;; ??? This combiner pattern does not work, because combine does not combine
;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
;; defined. Perhaps use a pseudo-reg for the T bit?
(define_insn "" (define_insn ""
[(set (reg:SI 18) [(set (reg:SI 18)
(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r") (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
...@@ -2108,17 +2104,10 @@ ...@@ -2108,17 +2104,10 @@
;; Misc insns ;; Misc insns
;; ------------------------------------------------------------------------ ;; ------------------------------------------------------------------------
;; ??? This combiner pattern does not work, because combine does not combine
;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
;; defined. Perhaps use a pseudo-reg for the T bit?
(define_insn "dect" (define_insn "dect"
[(parallel [(set (match_operand:SI 0 "arith_reg_operand" "=r") [(set (reg:SI 18)
(plus:SI (match_dup 0) (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
(const_int -1))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
(set (reg:SI 18)
(eq:SI (plus:SI (match_dup 0) (const_int -1))
(const_int 0)))])]
"TARGET_SH2" "TARGET_SH2"
"dt %0") "dt %0")
......
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