re PR target/10979 (ICE in subst_stack_regs_pat with -O -ffast-math and atan2)

	PR target/10979
	* config/i386/i386.md (atan2df3, atan2sf3, atan2xf3, atan2tf3):
	Changed to define_expand patterns that copy operand[1] to prevent
	it from being clobbered before emitting an atan2?f3_1 insn.
	(atan2df3_1, atan2sf3_1, atan2xf_1, atan2tf3_1): New define_insn
	patterns that actually specify the behaviour of x87's FPATAN.

	* gcc.dg/20030707-1.c: New testcase.

From-SVN: r69060

gcc/ChangeLog

+2003-07-07  Roger Sayle  <roger@eyesopen.com>
+
+	PR target/10979
+	* config/i386/i386.md (atan2df3, atan2sf3, atan2xf3, atan2tf3):
+	Changed to define_expand patterns that copy operand[1] to prevent
+	it from being clobbered before emitting an atan2?f3_1 insn.
+	(atan2df3_1, atan2sf3_1, atan2xf_1, atan2tf3_1): New define_insn
+	patterns that actually specify the behaviour of x87's FPATAN.
+
 2003-07-07  Jakub Jelinek  <jakub@redhat.com>
 
 	* config/rs6000/rs6000.c (rs6000_output_mi_thunk): Remove bogus

gcc/config/i386/i386.md

@@ -15582,7 +15582,7 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
-(define_insn "atan2df3"
+(define_insn "atan2df3_1"
   [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
 		   (unspec:DF [(match_operand:DF 2 "register_operand" "0")
 			       (match_operand:DF 1 "register_operand" "u")]
@@ -15594,7 +15594,20 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DF")])
 
-(define_insn "atan2sf3"
+(define_expand "atan2df3"
+  [(use (match_operand:DF 0 "register_operand" "=f"))
+   (use (match_operand:DF 2 "register_operand" "0"))
+   (use (match_operand:DF 1 "register_operand" "u"))]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  rtx copy = gen_reg_rtx (DFmode);
+  emit_move_insn (copy, operands[1]);
+  emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
+  DONE;
+}
+
+(define_insn "atan2sf3_1"
   [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
 		   (unspec:SF [(match_operand:SF 2 "register_operand" "0")
 			       (match_operand:SF 1 "register_operand" "u")]
@@ -15606,19 +15619,45 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "SF")])
 
-(define_insn "atan2xf3"
+(define_expand "atan2sf3"
+  [(use (match_operand:SF 0 "register_operand" "=f"))
+   (use (match_operand:SF 2 "register_operand" "0"))
+   (use (match_operand:SF 1 "register_operand" "u"))]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  rtx copy = gen_reg_rtx (SFmode);
+  emit_move_insn (copy, operands[1]);
+  emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
+  DONE;
+}
+
+(define_insn "atan2xf3_1"
   [(parallel [(set (match_operand:XF 0 "register_operand" "=f")
 		   (unspec:XF [(match_operand:XF 2 "register_operand" "0")
 			       (match_operand:XF 1 "register_operand" "u")]
 		    UNSPEC_FPATAN))
 	      (clobber (match_dup 1))])]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE"
   "fpatan"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
-(define_insn "atan2tf3"
+(define_expand "atan2xf3"
+  [(use (match_operand:XF 0 "register_operand" "=f"))
+   (use (match_operand:XF 2 "register_operand" "0"))
+   (use (match_operand:XF 1 "register_operand" "u"))]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE"
+{
+  rtx copy = gen_reg_rtx (XFmode);
+  emit_move_insn (copy, operands[1]);
+  emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
+  DONE;
+}
+
+(define_insn "atan2tf3_1"
   [(parallel [(set (match_operand:TF 0 "register_operand" "=f")
 		   (unspec:TF [(match_operand:TF 2 "register_operand" "0")
 			       (match_operand:TF 1 "register_operand" "u")]
@@ -15630,6 +15669,19 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
+(define_expand "atan2tf3"
+  [(use (match_operand:TF 0 "register_operand" "=f"))
+   (use (match_operand:TF 2 "register_operand" "0"))
+   (use (match_operand:TF 1 "register_operand" "u"))]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
+{
+  rtx copy = gen_reg_rtx (TFmode);
+  emit_move_insn (copy, operands[1]);
+  emit_insn (gen_atan2tf3_1 (operands[0], copy, operands[2]));
+  DONE;
+}
+
 (define_insn "*fyl2x_sfxf3"
   [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
 		   (unspec:SF [(match_operand:SF 2 "register_operand" "0")

gcc/testsuite/ChangeLog

 2003-07-07  Roger Sayle  <roger@eyesopen.com>
 
+	PR target/10979
+	* gcc.dg/20030707-1.c: New testcase.
+
+2003-07-07  Roger Sayle  <roger@eyesopen.com>
+
 	PR optimization/11059
 	* g++.dg/opt/emptyunion.C: New testcase.
 

gcc/testsuite/gcc.dg/20030707-1.c

+/* Derived from PR target/10979.  */
+/* This testcase used to ICE on x86.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+void t(double);
+double atan2(double,double);
+
+void temp(double *c)
+{
+  double c2 = 8;
+  double s2 = 0;
+  *c = atan2(s2,c2);
+  t(1/s2);
+}
+