Commit af93f7bf by Tom Wood

(define_function_unit): Change meaning to ISSUE-DELAY.

Merge FP_MUL, FP_DIV, and FP_SQRT into one function unit.

From-SVN: r1947
parent c8e18a2b
...@@ -123,7 +123,7 @@ ...@@ -123,7 +123,7 @@
;; Function units of the SPARC ;; Function units of the SPARC
;; (define_function_unit {name} {num-units} {n-users} {test} ;; (define_function_unit {name} {num-units} {n-users} {test}
;; {ready-delay} {busy-delay} [{conflict-list}]) ;; {ready-delay} {issue-delay} [{conflict-list}])
;; The integer ALU. ;; The integer ALU.
;; (Noted only for documentation; units that take one cycle do not need to ;; (Noted only for documentation; units that take one cycle do not need to
...@@ -133,7 +133,7 @@ ...@@ -133,7 +133,7 @@
;; (eq_attr "type" "unary,binary,move,address") 1 0) ;; (eq_attr "type" "unary,binary,move,address") 1 0)
;; Memory with load-delay of 1 (i.e., 2 cycle load). ;; Memory with load-delay of 1 (i.e., 2 cycle load).
(define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0) (define_function_unit "memory" 1 1 (eq_attr "type" "load,fpload") 2 0)
;; SPARC has two floating-point units: the FP ALU, ;; SPARC has two floating-point units: the FP ALU,
;; and the FP MUL/DIV/SQRT unit. ;; and the FP MUL/DIV/SQRT unit.
...@@ -154,10 +154,10 @@ ...@@ -154,10 +154,10 @@
;; The CY7C602 can only support 2 fp isnsn simultaneously. ;; The CY7C602 can only support 2 fp isnsn simultaneously.
;; More insns cause the chip to stall. ;; More insns cause the chip to stall.
(define_function_unit "fp_alu" 1 2 (eq_attr "type" "fp") 5 0) (define_function_unit "fp_alu" 1 1 (eq_attr "type" "fp") 5 0)
(define_function_unit "fp_mul" 1 2 (eq_attr "type" "fpmul") 7 0) (define_function_unit "fp_mds" 1 1 (eq_attr "type" "fpmul") 7 0)
(define_function_unit "fp_div" 1 2 (eq_attr "type" "fpdiv") 37 0) (define_function_unit "fp_mds" 1 1 (eq_attr "type" "fpdiv") 37 0)
(define_function_unit "fp_sqrt" 1 2 (eq_attr "type" "fpsqrt") 63 0) (define_function_unit "fp_mds" 1 1 (eq_attr "type" "fpsqrt") 63 0)
;; Compare instructions. ;; Compare instructions.
;; This controls RTL generation and register allocation. ;; This controls RTL generation and register allocation.
......
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