athlon.md, [...]: New files.

        * athlon.md, k6.md, pentium.md, ppro.md): New files.
        * i386.md: Move scheduling information into new files.

From-SVN: r53350

gcc/ChangeLog

@@ -62,6 +62,9 @@ doc:
 
 Thu May  9 11:50:09 2002  Jeffrey A Law  (law@cygnus.com)
 
+	* athlon.md, k6.md, pentium.md, ppro.md): New files.
+	* i386.md: Move scheduling information into new files.
+
 	* i386.md (type attribute): Add "rotate" for rotate insns.
 	(rotate insns): Set type to "rotate".
 	(various attributes and function units): Treat rotate like shift.

gcc/config/i386/athlon.md

+;; AMD Athlon Scheduling
+;; Copyright (C) 2002 Free Software Foundation, Inc.
+;;
+;; This file is part of GNU CC.
+;;
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.  */
+(define_attr "athlon_decode" "direct,vector"
+  (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
+	   (const_string "vector")
+         (and (eq_attr "type" "push")
+              (match_operand 1 "memory_operand" ""))
+	   (const_string "vector")
+         (and (eq_attr "type" "fmov")
+	      (and (eq_attr "memory" "load,store")
+		   (eq_attr "mode" "XF")))
+	   (const_string "vector")]
+	(const_string "direct")))
+
+;; The Athlon does contain three pipelined FP units, three integer units and
+;; three address generation units. 
+;;
+;; The predecode logic is determining boundaries of instructions in the 64
+;; byte cache line. So the cache line straddling problem of K6 might be issue
+;; here as well, but it is not noted in the documentation.
+;;
+;; Three DirectPath instructions decoders and only one VectorPath decoder
+;; is available. They can decode three DirectPath instructions or one VectorPath
+;; instruction per cycle.
+;; Decoded macro instructions are then passed to 72 entry instruction control
+;; unit, that passes
+;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
+;;
+;; The load/store queue unit is not attached to the schedulers but
+;; communicates with all the execution units separately instead.
+
+(define_function_unit "athlon_vectordec" 1 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "athlon_decode" "vector"))
+  1 1)
+
+(define_function_unit "athlon_directdec" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "athlon_decode" "direct"))
+  1 1)
+
+(define_function_unit "athlon_vectordec" 1 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "athlon_decode" "direct"))
+  1 1 [(eq_attr "athlon_decode" "vector")])
+
+(define_function_unit "athlon_ieu" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,rotate,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
+  1 1)
+
+(define_function_unit "athlon_ieu" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "str"))
+  15 15)
+
+(define_function_unit "athlon_ieu" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "imul"))
+  5 0)
+
+(define_function_unit "athlon_ieu" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "idiv"))
+  42 0)
+
+(define_function_unit "athlon_muldiv" 1 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "imul"))
+  5 0)
+
+(define_function_unit "athlon_muldiv" 1 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "idiv"))
+  42 42)
+
+(define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
+  (cond [(eq_attr "type" "fop,fcmp,fistp")
+	   (const_string "add")
+         (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
+	   (const_string "mul")
+	 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
+	   (const_string "store")
+	 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
+	   (const_string "any")
+         (and (eq_attr "type" "fmov")
+              (ior (match_operand:SI 1 "register_operand" "")
+                   (match_operand 1 "immediate_operand" "")))
+	   (const_string "store")
+         (eq_attr "type" "fmov")
+	   (const_string "muladd")]
+	(const_string "none")))
+
+;; We use latencies 1 for definitions.  This is OK to model colisions
+;; in execution units.  The real latencies are modeled in the "fp" pipeline.
+
+;; fsin, fcos: 96-192
+;; fsincos: 107-211
+;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
+(define_function_unit "athlon_fp" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "fpspc"))
+  100 1)
+
+;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
+(define_function_unit "athlon_fp" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "fdiv"))
+  24 1)
+
+(define_function_unit "athlon_fp" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "fop,fmul,fistp"))
+  4 1)
+
+;; XFmode loads are slow.
+;; XFmode store is slow too (8 cycles), but we don't need to model it, because
+;; there are no dependent instructions.
+
+(define_function_unit "athlon_fp" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (and (eq_attr "type" "fmov")
+	    (and (eq_attr "memory" "load")
+		 (eq_attr "mode" "XF"))))
+  10 1)
+
+(define_function_unit "athlon_fp" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "fmov,fsgn"))
+  2 1)
+
+;; fcmp and ftst instructions
+(define_function_unit "athlon_fp" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (and (eq_attr "type" "fcmp")
+	    (eq_attr "athlon_decode" "direct")))
+  3 1)
+
+;; fcmpi instructions.
+(define_function_unit "athlon_fp" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (and (eq_attr "type" "fcmp")
+	    (eq_attr "athlon_decode" "vector")))
+  3 1)
+
+(define_function_unit "athlon_fp" 3 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "type" "fcmov"))
+  7 1)
+
+(define_function_unit "athlon_fp_mul" 1 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "athlon_fpunits" "mul"))
+  1 1)
+
+(define_function_unit "athlon_fp_add" 1 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "athlon_fpunits" "add"))
+  1 1)
+
+(define_function_unit "athlon_fp_muladd" 2 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "athlon_fpunits" "muladd,mul,add"))
+  1 1)
+
+(define_function_unit "athlon_fp_store" 1 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "athlon_fpunits" "store"))
+  1 1)
+
+;; We don't need to model the Address Generation Unit, since we don't model
+;; the re-order buffer yet and thus we never schedule more than three operations
+;; at time.  Later we may want to experiment with MD_SCHED macros modeling the
+;; decoders independently on the functional units.
+
+;(define_function_unit "athlon_agu" 3 0
+;  (and (eq_attr "cpu" "athlon")
+;       (and (eq_attr "memory" "!none")
+;            (eq_attr "athlon_fpunits" "none")))
+;  1 1)
+
+;; Model load unit to avoid too long sequences of loads.  We don't need to
+;; model store queue, since it is hardly going to be bottleneck.
+
+(define_function_unit "athlon_load" 2 0
+  (and (eq_attr "cpu" "athlon")
+       (eq_attr "memory" "load,both"))
+  1 1)
+

gcc/config/i386/k6.md

+;; AMD K6/K6-2 Scheduling
+;; Copyright (C) 2002 ;; Free Software Foundation, Inc.
+;;
+;; This file is part of GNU CC.
+;;
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.  */
+;;
+;; The K6 has similar architecture to PPro.  Important difference is, that
+;; there are only two decoders and they seems to be much slower than execution
+;; units.  So we have to pay much more attention to proper decoding for
+;; schedulers.  We share most of scheduler code for PPro in i386.c
+;;
+;; The fp unit is not pipelined and do one operation per two cycles including
+;; the FXCH.
+;;
+;; alu	  describes both ALU units (ALU-X and ALU-Y).
+;; alux   describes X alu unit
+;; fpu    describes FPU unit
+;; load   describes load unit.
+;; branch describes branch unit.
+;; store  decsribes store unit.  This unit is not modelled completely and only
+;;        used to model lea operation.  Otherwise it lie outside of the critical
+;;        path.
+;;
+;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
+
+;; The decoder specification is in the PPro section above!
+
+;; Shift instructions and certain arithmetic are issued only to X pipe.
+(define_function_unit "k6_alux" 1 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "ishift,rotate,alu1,negnot,cld"))
+  1 1)
+
+;; The QI mode arithmetic is issued to X pipe only.
+(define_function_unit "k6_alux" 1 0
+  (and (eq_attr "cpu" "k6")
+       (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
+	    (match_operand:QI 0 "general_operand" "")))
+  1 1)
+
+(define_function_unit "k6_alu" 2 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "ishift,rotate,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
+  1 1)
+
+(define_function_unit "k6_alu" 2 0
+  (and (eq_attr "cpu" "k6")
+       (and (eq_attr "type" "imov")
+       	    (eq_attr "memory" "none")))
+  1 1)
+
+(define_function_unit "k6_branch" 1 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "call,callv,ibr"))
+  1 1)
+
+;; Load unit have two cycle latency, but we take care for it in adjust_cost
+(define_function_unit "k6_load" 1 0
+  (and (eq_attr "cpu" "k6")
+       (ior (eq_attr "type" "pop")
+	    (eq_attr "memory" "load,both")))
+  1 1)
+
+(define_function_unit "k6_load" 1 0
+  (and (eq_attr "cpu" "k6")
+       (and (eq_attr "type" "str")
+	    (eq_attr "memory" "load,both")))
+  10 10)
+
+;; Lea have two instructions, so latency is probably 2
+(define_function_unit "k6_store" 1 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "lea"))
+  2 1)
+
+(define_function_unit "k6_store" 1 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "str"))
+  10 10)
+
+(define_function_unit "k6_store" 1 0
+  (and (eq_attr "cpu" "k6")
+       (ior (eq_attr "type" "push")
+	    (eq_attr "memory" "store,both")))
+  1 1)
+
+(define_function_unit "k6_fpu" 1 1
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "fop,fmov,fcmp,fistp"))
+  2 2)
+
+(define_function_unit "k6_fpu" 1 1
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "fmul"))
+  2 2)
+
+;; ??? Guess
+(define_function_unit "k6_fpu" 1 1
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "fdiv,fpspc"))
+  56 56)
+
+(define_function_unit "k6_alu" 2 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "imul"))
+  2 2)
+
+(define_function_unit "k6_alux" 1 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "imul"))
+  2 2)
+
+;; ??? Guess
+(define_function_unit "k6_alu" 2 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "idiv"))
+  17 17)
+
+(define_function_unit "k6_alux" 1 0
+  (and (eq_attr "cpu" "k6")
+       (eq_attr "type" "idiv"))
+  17 17)

gcc/config/i386/ppro.md

+;; Pentium Pro/PII Scheduling
+;; Copyright (C) 2002 Free Software Foundation, Inc.
+;;
+;; This file is part of GNU CC.
+;;
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.  */
+
+;; Categorize how many uops an ia32 instruction evaluates to:
+;;   one --  an instruction with 1 uop can be decoded by any of the
+;;           three decoders.
+;;   few --  an instruction with 1 to 4 uops can be decoded only by 
+;;	     decoder 0.
+;;   many -- a complex instruction may take an unspecified number of
+;;	     cycles to decode in decoder 0.
+
+(define_attr "ppro_uops" "one,few,many"
+  (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
+	   (const_string "many")
+	 (eq_attr "type" "icmov,fcmov,str,cld")
+	   (const_string "few")
+	 (eq_attr "type" "imov")
+	   (if_then_else (eq_attr "memory" "store,both")
+	     (const_string "few")
+	     (const_string "one"))
+	 (eq_attr "memory" "!none")
+	   (const_string "few")
+	]
+	(const_string "one")))
+
+;;
+;; The PPro has an out-of-order core, but the instruction decoders are
+;; naturally in-order and asymmetric.  We get best performance by scheduling
+;; for the decoders, for in doing so we give the oo execution unit the 
+;; most choices.
+;;
+;; Rough readiness numbers.  Fine tuning happens in i386.c.
+;;
+;; p0	describes port 0.
+;; p01	describes ports 0 and 1 as a pair; alu insns can issue to either.
+;; p2	describes port 2 for loads.
+;; p34	describes ports 3 and 4 for stores.
+;; fpu	describes the fpu accessed via port 0. 
+;;	??? It is less than clear if there are separate fadd and fmul units
+;;	that could operate in parallel.
+;;
+;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
+
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "ishift,rotate,lea,ibr,cld"))
+  1 1)
+
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "imul"))
+  4 1)
+
+;; ??? Does the divider lock out the pipe while it works,
+;; or is there a disconnected unit?
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "idiv"))
+  17 17)
+
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fop,fsgn,fistp"))
+  3 1)
+
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fcmov"))
+  2 1)
+
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fcmp"))
+  1 1)
+
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fmov"))
+  1 1)
+
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fmul"))
+  5 1)
+
+(define_function_unit "ppro_p0" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fdiv,fpspc"))
+  56 1)
+
+(define_function_unit "ppro_p01" 2 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "!imov,fmov"))
+  1 1)
+
+(define_function_unit "ppro_p01" 2 0
+  (and (and (eq_attr "cpu" "pentiumpro")
+            (eq_attr "type" "imov,fmov"))
+       (eq_attr "memory" "none"))
+  1 1)
+
+(define_function_unit "ppro_p2" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (ior (eq_attr "type" "pop")
+	    (eq_attr "memory" "load,both")))
+  3 1)
+
+(define_function_unit "ppro_p34" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (ior (eq_attr "type" "push")
+	    (eq_attr "memory" "store,both")))
+  1 1)
+
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fop,fsgn,fmov,fcmp,fcmov,fistp"))
+  1 1)
+
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fmul"))
+  5 2)
+
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "fdiv,fpspc"))
+  56 56)
+
+;; imul uses the fpu.  ??? does it have the same throughput as fmul?
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "cpu" "pentiumpro")
+       (eq_attr "type" "imul"))
+  4 1)