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riscv-gcc-1
Commit ae4b4a02 by Aldy Hernandez Committed by Aldy Hernandez
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extend.texi: Warn about unsupported usage of altivec builtins. 

2002-01-31  Aldy Hernandez  <aldyh@redhat.com>

        * doc/extend.texi: Warn about unsupported usage of altivec
        builtins.

        * config/rs6000/rs6000.md (altivec_vcmp*_p): Remove.
        (altivec_predicate_*): New.

        * config/rs6000/altivec.h: Rewrite predicates to use new builtins.
        Add C++ version of vec_*() functions.

        * config/rs6000/rs6000.c (bdesc_altivec_preds): New.
        (bdesc_2arg): Remove altivec predicates.
        (altivec_expand_builtin): Handle predicates.
        (altivec_init_builtins): Handle predicates.
        (altivec_expand_predicate_builtin): New.

From-SVN: r49500
parent f6bcf44c
Showing with 270 additions and 111 deletions
gcc/ChangeLog
2002-02-05 Aldy Hernandez <aldyh@redhat.com>
* doc/extend.texi: Warn about unsupported usage of altivec
builtins.
* config/rs6000/rs6000.md (altivec_vcmp*_p): Remove.
(altivec_predicate_*): New.
* config/rs6000/altivec.h: Rewrite predicates to use new builtins.
Add C++ version of vec_*() functions.
* config/rs6000/rs6000.c (bdesc_altivec_preds): New.
(bdesc_2arg): Remove altivec predicates.
(altivec_expand_builtin): Handle predicates.
(altivec_init_builtins): Handle predicates.
(altivec_expand_predicate_builtin): New.
2002-02-04 John David Anglin <dave@hiauly1.hia.nrc.ca>
* pa.c (DO_FRAME_NOTES): Move forward.
......
gcc/config/rs6000/altivec.h
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/rs6000/rs6000.c
......@@ -163,6 +163,7 @@ static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int
static rtx altivec_expand_builtin PARAMS ((tree, rtx));
static rtx altivec_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx));
static rtx altivec_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx));
static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx));
static rtx altivec_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx));
static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree));
static void rs6000_parse_abi_options PARAMS ((void));
......@@ -3352,19 +3353,34 @@ static const struct builtin_description bdesc_2arg[] =
{ MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
{ MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp_p, "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp_p, "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb_p, "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh_p, "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw_p, "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp_p, "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp_p, "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb_p, "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh_p, "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw_p, "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub_p, "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh_p, "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw_p, "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
};
/* AltiVec predicates. */
struct builtin_description_predicates
{
const unsigned int mask;
const enum insn_code icode;
const char *opcode;
const char *const name;
const enum rs6000_builtins code;
};
static const struct builtin_description_predicates bdesc_altivec_preds[] =
{
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
{ MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
};
/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
......@@ -3422,6 +3438,7 @@ altivec_expand_unop_builtin (icode, arglist, target)
return target;
}
static rtx
altivec_expand_binop_builtin (icode, arglist, target)
enum insn_code icode;
......@@ -3460,6 +3477,87 @@ altivec_expand_binop_builtin (icode, arglist, target)
}
static rtx
altivec_expand_predicate_builtin (icode, opcode, arglist, target)
enum insn_code icode;
const char *opcode;
tree arglist;
rtx target;
{
rtx pat, scratch;
tree cr6_form = TREE_VALUE (arglist);
tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
enum machine_mode tmode = SImode;
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
enum machine_mode mode1 = insn_data[icode].operand[2].mode;
int cr6_form_int;
if (TREE_CODE (cr6_form) != INTEGER_CST)
{
error ("argument 1 of __builtin_altivec_predicate must be a constant");
return NULL_RTX;
}
else
cr6_form_int = TREE_INT_CST_LOW (cr6_form);
if (mode0 != mode1)
abort ();
/* If we have invalid arguments, bail out before generating bad rtl. */
if (arg0 == error_mark_node || arg1 == error_mark_node)
return NULL_RTX;
if (target == 0
|| GET_MODE (target) != tmode
|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
target = gen_reg_rtx (tmode);
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
op0 = copy_to_mode_reg (mode0, op0);
if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
op1 = copy_to_mode_reg (mode1, op1);
scratch = gen_reg_rtx (mode0);
pat = GEN_FCN (icode) (scratch, op0, op1,
gen_rtx (SYMBOL_REF, Pmode, opcode));
if (! pat)
return 0;
emit_insn (pat);
/* The vec_any* and vec_all* predicates use the same opcodes for two
different operations, but the bits in CR6 will be different
depending on what information we want. So we have to play tricks
with CR6 to get the right bits out.
If you think this is disgusting, look at the specs for the
AltiVec predicates. */
switch (cr6_form_int)
{
case 0:
emit_insn (gen_cr6_test_for_zero (target));
break;
case 1:
emit_insn (gen_cr6_test_for_zero_reverse (target));
break;
case 2:
emit_insn (gen_cr6_test_for_lt (target));
break;
case 3:
emit_insn (gen_cr6_test_for_lt_reverse (target));
break;
default:
error ("argument 1 of __builtin_altivec_predicate is out of range");
break;
}
return target;
}
static rtx
altivec_expand_stv_builtin (icode, arglist)
enum insn_code icode;
tree arglist;
......@@ -3543,6 +3641,7 @@ altivec_expand_builtin (exp, target)
rtx target;
{
struct builtin_description *d;
struct builtin_description_predicates *dp;
size_t i;
enum insn_code icode;
tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
......@@ -3830,6 +3929,12 @@ altivec_expand_builtin (exp, target)
if (d->code == fcode)
return altivec_expand_binop_builtin (d->icode, arglist, target);
/* Expand the AltiVec predicates. */
dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
for (i = 0; i < sizeof (bdesc_altivec_preds) / sizeof *dp; i++, dp++)
if (dp->code == fcode)
return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
/* LV* are funky. We initialized them differently. */
switch (fcode)
{
......@@ -3899,7 +4004,8 @@ rs6000_init_builtins ()
static void
altivec_init_builtins (void)
{
struct builtin_description * d;
struct builtin_description *d;
struct builtin_description_predicates *dp;
size_t i;
tree endlink = void_list_node;
......@@ -4265,6 +4371,38 @@ altivec_init_builtins (void)
tree_cons (NULL_TREE, V16QI_type_node,
endlink)));
tree int_ftype_int_v4si_v4si
= build_function_type
(integer_type_node,
tree_cons (NULL_TREE, integer_type_node,
tree_cons (NULL_TREE, V4SI_type_node,
tree_cons (NULL_TREE, V4SI_type_node,
endlink))));
tree int_ftype_int_v4sf_v4sf
= build_function_type
(integer_type_node,
tree_cons (NULL_TREE, integer_type_node,
tree_cons (NULL_TREE, V4SF_type_node,
tree_cons (NULL_TREE, V4SF_type_node,
endlink))));
tree int_ftype_int_v8hi_v8hi
= build_function_type
(integer_type_node,
tree_cons (NULL_TREE, integer_type_node,
tree_cons (NULL_TREE, V8HI_type_node,
tree_cons (NULL_TREE, V8HI_type_node,
endlink))));
tree int_ftype_int_v16qi_v16qi
= build_function_type
(integer_type_node,
tree_cons (NULL_TREE, integer_type_node,
tree_cons (NULL_TREE, V16QI_type_node,
tree_cons (NULL_TREE, V16QI_type_node,
endlink))));
tree v16qi_ftype_int_pvoid
= build_function_type (V16QI_type_node,
tree_cons (NULL_TREE, integer_type_node,
......@@ -4412,6 +4550,36 @@ altivec_init_builtins (void)
for (i = 0; i < sizeof (bdesc_dst) / sizeof *d; i++, d++)
def_builtin (d->mask, d->name, void_ftype_pvoid_int_char, d->code);
/* Initialize the predicates. */
dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
for (i = 0; i < sizeof (bdesc_altivec_preds) / sizeof *dp; i++, dp++)
{
enum machine_mode mode1;
tree type;
mode1 = insn_data[dp->icode].operand[1].mode;
switch (mode1)
{
case V4SImode:
type = int_ftype_int_v4si_v4si;
break;
case V8HImode:
type = int_ftype_int_v8hi_v8hi;
break;
case V16QImode:
type = int_ftype_int_v16qi_v16qi;
break;
case V4SFmode:
type = int_ftype_int_v4sf_v4sf;
break;
default:
abort ();
}
def_builtin (dp->mask, dp->name, type, dp->code);
}
/* Add the simple binary operators. */
d = (struct builtin_description *) bdesc_2arg;
for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
......
gcc/config/rs6000/rs6000.h
......@@ -2938,19 +2938,6 @@ enum rs6000_builtins
ALTIVEC_BUILTIN_VUPKLSB,
ALTIVEC_BUILTIN_VUPKLPX,
ALTIVEC_BUILTIN_VUPKLSH,
ALTIVEC_BUILTIN_VCMPBFP_P,
ALTIVEC_BUILTIN_VCMPEQFP_P,
ALTIVEC_BUILTIN_VCMPEQUB_P,
ALTIVEC_BUILTIN_VCMPEQUH_P,
ALTIVEC_BUILTIN_VCMPEQUW_P,
ALTIVEC_BUILTIN_VCMPGEFP_P,
ALTIVEC_BUILTIN_VCMPGTFP_P,
ALTIVEC_BUILTIN_VCMPGTSB_P,
ALTIVEC_BUILTIN_VCMPGTSH_P,
ALTIVEC_BUILTIN_VCMPGTSW_P,
ALTIVEC_BUILTIN_VCMPGTUB_P,
ALTIVEC_BUILTIN_VCMPGTUH_P,
ALTIVEC_BUILTIN_VCMPGTUW_P,
ALTIVEC_BUILTIN_MTVSCR,
ALTIVEC_BUILTIN_MFVSCR,
ALTIVEC_BUILTIN_DSSALL,
......@@ -2970,5 +2957,18 @@ enum rs6000_builtins
ALTIVEC_BUILTIN_STVEBX,
ALTIVEC_BUILTIN_STVEHX,
ALTIVEC_BUILTIN_STVEWX,
ALTIVEC_BUILTIN_STVXL
ALTIVEC_BUILTIN_STVXL,
ALTIVEC_BUILTIN_VCMPBFP_P,
ALTIVEC_BUILTIN_VCMPEQFP_P,
ALTIVEC_BUILTIN_VCMPEQUB_P,
ALTIVEC_BUILTIN_VCMPEQUH_P,
ALTIVEC_BUILTIN_VCMPEQUW_P,
ALTIVEC_BUILTIN_VCMPGEFP_P,
ALTIVEC_BUILTIN_VCMPGTFP_P,
ALTIVEC_BUILTIN_VCMPGTSB_P,
ALTIVEC_BUILTIN_VCMPGTSH_P,
ALTIVEC_BUILTIN_VCMPGTSW_P,
ALTIVEC_BUILTIN_VCMPGTUB_P,
ALTIVEC_BUILTIN_VCMPGTUH_P,
ALTIVEC_BUILTIN_VCMPGTUW_P
};
gcc/config/rs6000/rs6000.md
......@@ -15318,110 +15318,79 @@
;; AltiVec predicates.
(define_insn "altivec_vcmpequb_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 173))]
"TARGET_ALTIVEC"
"vcmpequb. %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpequh_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 174))]
"TARGET_ALTIVEC"
"vcmpequh. %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpequw_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 175))]
"TARGET_ALTIVEC"
"vcmpequw. %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpeqfp_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 176))]
(define_expand "cr6_test_for_zero"
[(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (reg:CC 74)
(const_int 0)))]
"TARGET_ALTIVEC"
"vcmpeqfp. %0,%1,%2"
[(set_attr "type" "veccmp")])
"")
(define_insn "altivec_vcmpgtub_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 177))]
(define_expand "cr6_test_for_zero_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (reg:CC 74)
(const_int 0)))
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
"TARGET_ALTIVEC"
"vcmpgtub. %0,%1,%2"
[(set_attr "type" "veccmp")])
"")
(define_insn "altivec_vcmpgtsb_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")] 178))]
(define_expand "cr6_test_for_lt"
[(set (match_operand:SI 0 "register_operand" "=r")
(lt:SI (reg:CC 74)
(const_int 0)))]
"TARGET_ALTIVEC"
"vcmpgtsb. %0,%1,%2"
[(set_attr "type" "veccmp")])
"")
(define_insn "altivec_vcmpgtuw_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 179))]
(define_expand "cr6_test_for_lt_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
(lt:SI (reg:CC 74)
(const_int 0)))
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
"TARGET_ALTIVEC"
"vcmpgtuw. %0,%1,%2"
[(set_attr "type" "veccmp")])
"")
(define_insn "altivec_vcmpgtsw_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 180))]
"TARGET_ALTIVEC"
"vcmpgtsw. %0,%1,%2"
[(set_attr "type" "veccmp")])
;; We can get away with generating the opcode on the fly (%3 below)
;; because all the predicates have the same scheduling parameters.
(define_insn "altivec_vcmpgefp_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 181))]
(define_insn "altivec_predicate_v4si"
[(set (reg:CC 74)
(unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")
(match_operand 3 "any_operand" "")] 173))
(clobber (match_scratch:V4SI 0 "=v"))]
"TARGET_ALTIVEC"
"vcmpgefp. %0,%1,%2"
"%3 %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpgtfp_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 182))]
(define_insn "altivec_predicate_v4sf"
[(set (reg:CC 74)
(unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
(match_operand 3 "any_operand" "")] 174))
(clobber (match_scratch:V4SF 0 "=v"))]
"TARGET_ALTIVEC"
"vcmpgtfp. %0,%1,%2"
"%3 %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpbfp_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")] 183))]
(define_insn "altivec_predicate_v8hi"
[(set (reg:CC 74)
(unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
(match_operand 3 "any_operand" "")] 175))
(clobber (match_scratch:V8HI 0 "=v"))]
"TARGET_ALTIVEC"
"vcmpbfp. %0,%1,%2"
"%3 %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpgtuh_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 184))]
(define_insn "altivec_predicate_v16qi"
[(set (reg:CC 74)
(unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")
(match_operand 3 "any_operand" "")] 175))
(clobber (match_scratch:V16QI 0 "=v"))]
"TARGET_ALTIVEC"
"vcmpgtuh. %0,%1,%2"
"%3 %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpgtsh_p"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 185))]
"TARGET_ALTIVEC"
"vcmpgtsh. %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_mtvscr"
[(unspec [(match_operand:V4SI 0 "register_operand" "v")] 186)]
"TARGET_ALTIVEC"
......
gcc/doc/extend.texi
......@@ -4889,6 +4889,11 @@ The following functions are made available by including
@option{-mabi=altivec}. The functions implement the functionality
described in Motorola's AltiVec Programming Interface Manual.
@emph{Note:} Only the @code{<altivec.h>} interface is supported.
Internally, GCC uses built-in functions to achieve the functionality in
the aforementioned header file, but they are not supported and are
subject to change without notice.
@smallexample
vector signed char vec_abs (vector signed char, vector signed char);
vector signed short vec_abs (vector signed short, vector signed short);
......
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