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riscv-gcc-1
Commit ad6aec71 by Kyrylo Tkachov
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Commit missing Changelogs for PR target/82518 fix. 

From-SVN: r258708
parent 1f4d266b
Showing with 13 additions and 0 deletions
gcc/ChangeLog
...@@ -41,6 +41,12 @@ ...@@ -41,6 +41,12 @@
(altivec_expand_builtin): Likewise. (altivec_expand_builtin): Likewise.
* config/rs6000/vector.md: Likewise. * config/rs6000/vector.md: Likewise.
2018-03-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/82518
* config/arm/arm.c (arm_array_mode_supported_p): Return false for
BYTES_BIG_ENDIAN.
2018-03-20 Richard Biener <rguenther@suse.de> 2018-03-20 Richard Biener <rguenther@suse.de>
PR target/84986 PR target/84986
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gcc/testsuite/ChangeLog
...@@ -33,6 +33,13 @@ ...@@ -33,6 +33,13 @@
PR c++/84978, ICE with NRVO. PR c++/84978, ICE with NRVO.
* g++.dg/opt/nrv19.C: New test. * g++.dg/opt/nrv19.C: New test.
2018-03-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/82518
* lib/target-supports.exp (check_effective_target_vect_load_lanes):
Disable for armeb targets.
* gcc.target/arm/pr82518.c: New test.
2018-03-20 Nathan Sidwell <nathan@acm.org> 2018-03-20 Nathan Sidwell <nathan@acm.org>
PR c++/84962 PR c++/84962
......
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