rs6000: Delete meaningless arguments to define_{expand,split,peephole2}

This removes the (usually empty) constraint arguments to define_expand,
define_split, and define_peephole2: this argument is meaningless and
just noise.


	* config/rs6000/altivec.md: Delete contraint arguments to
	define_expand, define_split, and define_peephole2, and in
	define_insn_and_split if always unused.
	* config/rs6000/darwin.md: Ditto.
	* config/rs6000/dfp.md: Ditto.
	* config/rs6000/rs6000.md: Ditto.
	* config/rs6000/sync.md: Ditto.
	* config/rs6000/vector.md: Ditto.
	* config/rs6000/vsx.md: Ditto.

From-SVN: r257890

gcc/ChangeLog

 2018-02-21  Segher Boessenkool  <segher@kernel.crashing.org>
 
+	* config/rs6000/altivec.md: Delete contraint arguments to
+	define_expand, define_split, and define_peephole2, and in
+	define_insn_and_split if always unused.
+	* config/rs6000/darwin.md: Ditto.
+	* config/rs6000/dfp.md: Ditto.
+	* config/rs6000/rs6000.md: Ditto.
+	* config/rs6000/sync.md: Ditto.
+	* config/rs6000/vector.md: Ditto.
+	* config/rs6000/vsx.md: Ditto.
+
+2018-02-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
 	* config/rs6000/altivec.md: Write output control strings as braced
 	blocks instead of double-quoted strings.
 	* config/rs6000/darwin.md: Ditto.

gcc/config/rs6000/darwin.md

@@ -171,8 +171,8 @@ You should have received a copy of the GNU General Public License
 
 ;; Mach-O PIC trickery.
 (define_expand "macho_high"
-  [(set (match_operand 0 "" "")
-	(high (match_operand 1 "" "")))]
+  [(set (match_operand 0 "")
+	(high (match_operand 1 "")))]
   "TARGET_MACHO"
 {
   if (TARGET_64BIT)
@@ -197,9 +197,9 @@ You should have received a copy of the GNU General Public License
   "lis %0,ha16(%1)")
 
 (define_expand "macho_low"
-  [(set (match_operand 0 "" "")
-	(lo_sum (match_operand 1 "" "")
-		   (match_operand 2 "" "")))]
+  [(set (match_operand 0 "")
+	(lo_sum (match_operand 1 "")
+		   (match_operand 2 "")))]
    "TARGET_MACHO"
 {
   if (TARGET_64BIT)
@@ -225,10 +225,10 @@ You should have received a copy of the GNU General Public License
    "la %0,lo16(%2)(%1)")
 
 (define_split
-  [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
-			 (match_operand:DI 1 "short_cint_operand" "")))
-	(match_operand:V4SI 2 "register_operand" ""))
-   (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+  [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand")
+			 (match_operand:DI 1 "short_cint_operand")))
+	(match_operand:V4SI 2 "register_operand"))
+   (clobber (match_operand:DI 3 "gpc_reg_operand"))]
   "TARGET_MACHO && TARGET_64BIT"
   [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
    (set (mem:V4SI (match_dup 3))
@@ -237,7 +237,7 @@ You should have received a copy of the GNU General Public License
 
 (define_expand "load_macho_picbase"
   [(set (reg:SI LR_REGNO)
-        (unspec [(match_operand 0 "" "")]
+        (unspec [(match_operand 0 "")]
                    UNSPEC_LD_MPIC))]
   "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
 {
@@ -284,10 +284,10 @@ You should have received a copy of the GNU General Public License
    (set_attr "length" "4")])
 
 (define_expand "macho_correct_pic"
-  [(set (match_operand 0 "" "")
-	(plus (match_operand 1 "" "")
-		 (unspec [(match_operand 2 "" "")
-			     (match_operand 3 "" "")]
+  [(set (match_operand 0 "")
+	(plus (match_operand 1 "")
+		 (unspec [(match_operand 2 "")
+			     (match_operand 3 "")]
 			    UNSPEC_MPIC_CORRECT)))]
   "DEFAULT_ABI == ABI_DARWIN"
 {
@@ -383,7 +383,7 @@ You should have received a copy of the GNU General Public License
 
 (define_expand "reload_macho_picbase"
   [(set (reg:SI LR_REGNO)
-        (unspec [(match_operand 0 "" "")]
+        (unspec [(match_operand 0 "")]
                    UNSPEC_RELD_MPIC))]
   "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
 {

gcc/config/rs6000/dfp.md

@@ -344,11 +344,11 @@
   [(set (match_dup 3)
 	(compare:CCFP
          (unspec:D64_D128
-	  [(match_operand:SI 1 "const_int_operand" "n")
-	   (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
+	  [(match_operand:SI 1 "const_int_operand")
+	   (match_operand:D64_D128 2 "gpc_reg_operand")]
 	  UNSPEC_DTSTSFI)
 	 (match_dup 4)))
-   (set (match_operand:SI 0 "register_operand" "")
+   (set (match_operand:SI 0 "register_operand")
    	(DFP_TEST:SI (match_dup 3)
 		     (const_int 0)))
   ]

gcc/config/rs6000/sync.md

@@ -38,7 +38,7 @@
    (ior "logical_operand") (xor "logical_operand") (and "and_operand")])
 
 (define_expand "mem_thread_fence"
-  [(match_operand:SI 0 "const_int_operand" "")]		;; model
+  [(match_operand:SI 0 "const_int_operand")]		;; model
   ""
 {
   enum memmodel model = memmodel_base (INTVAL (operands[0]));
@@ -136,9 +136,9 @@
    (set_attr "length" "4")])
 
 (define_expand "atomic_load<mode>"
-  [(set (match_operand:AINT 0 "register_operand" "")		;; output
-	(match_operand:AINT 1 "memory_operand" ""))		;; memory
-   (use (match_operand:SI 2 "const_int_operand" ""))]		;; model
+  [(set (match_operand:AINT 0 "register_operand")		;; output
+	(match_operand:AINT 1 "memory_operand"))		;; memory
+   (use (match_operand:SI 2 "const_int_operand"))]		;; model
   ""
 {
   if (<MODE>mode == TImode && !TARGET_SYNC_TI)
@@ -200,9 +200,9 @@
    (set_attr "length" "4")])
 
 (define_expand "atomic_store<mode>"
-  [(set (match_operand:AINT 0 "memory_operand" "")		;; memory
-	(match_operand:AINT 1 "register_operand" ""))		;; input
-   (use (match_operand:SI 2 "const_int_operand" ""))]		;; model
+  [(set (match_operand:AINT 0 "memory_operand")		;; memory
+	(match_operand:AINT 1 "register_operand"))	;; input
+   (use (match_operand:SI 2 "const_int_operand"))]	;; model
   ""
 {
   if (<MODE>mode == TImode && !TARGET_SYNC_TI)
@@ -287,8 +287,8 @@
 ;; is indexed or indirect before register allocation.
 
 (define_expand "load_lockedti"
-  [(use (match_operand:TI 0 "quad_int_reg_operand" ""))
-   (use (match_operand:TI 1 "memory_operand" ""))]
+  [(use (match_operand:TI 0 "quad_int_reg_operand"))
+   (use (match_operand:TI 1 "memory_operand"))]
   "TARGET_SYNC_TI"
 {
   rtx op0 = operands[0];
@@ -341,9 +341,9 @@
 ;; is indexed or indirect before register allocation.
 
 (define_expand "store_conditionalti"
-  [(use (match_operand:CC 0 "cc_reg_operand" ""))
-   (use (match_operand:TI 1 "memory_operand" ""))
-   (use (match_operand:TI 2 "quad_int_reg_operand" ""))]
+  [(use (match_operand:CC 0 "cc_reg_operand"))
+   (use (match_operand:TI 1 "memory_operand"))
+   (use (match_operand:TI 2 "quad_int_reg_operand"))]
   "TARGET_SYNC_TI"
 {
   rtx op0 = operands[0];
@@ -385,14 +385,14 @@
   [(set_attr "type" "store_c")])
 
 (define_expand "atomic_compare_and_swap<mode>"
-  [(match_operand:SI 0 "int_reg_operand" "")		;; bool out
-   (match_operand:AINT 1 "int_reg_operand" "")		;; val out
-   (match_operand:AINT 2 "memory_operand" "")		;; memory
-   (match_operand:AINT 3 "reg_or_short_operand" "")	;; expected
-   (match_operand:AINT 4 "int_reg_operand" "")		;; desired
-   (match_operand:SI 5 "const_int_operand" "")		;; is_weak
-   (match_operand:SI 6 "const_int_operand" "")		;; model succ
-   (match_operand:SI 7 "const_int_operand" "")]		;; model fail
+  [(match_operand:SI 0 "int_reg_operand")		;; bool out
+   (match_operand:AINT 1 "int_reg_operand")		;; val out
+   (match_operand:AINT 2 "memory_operand")		;; memory
+   (match_operand:AINT 3 "reg_or_short_operand")	;; expected
+   (match_operand:AINT 4 "int_reg_operand")		;; desired
+   (match_operand:SI 5 "const_int_operand")		;; is_weak
+   (match_operand:SI 6 "const_int_operand")		;; model succ
+   (match_operand:SI 7 "const_int_operand")]		;; model fail
   ""
 {
   rs6000_expand_atomic_compare_and_swap (operands);
@@ -400,10 +400,10 @@
 })
 
 (define_expand "atomic_exchange<mode>"
-  [(match_operand:AINT 0 "int_reg_operand" "")		;; output
-   (match_operand:AINT 1 "memory_operand" "")		;; memory
-   (match_operand:AINT 2 "int_reg_operand" "")		;; input
-   (match_operand:SI 3 "const_int_operand" "")]		;; model
+  [(match_operand:AINT 0 "int_reg_operand")		;; output
+   (match_operand:AINT 1 "memory_operand")		;; memory
+   (match_operand:AINT 2 "int_reg_operand")		;; input
+   (match_operand:SI 3 "const_int_operand")]		;; model
   ""
 {
   rs6000_expand_atomic_exchange (operands);
@@ -411,10 +411,10 @@
 })
 
 (define_expand "atomic_<fetchop_name><mode>"
-  [(match_operand:AINT 0 "memory_operand" "")		;; memory
+  [(match_operand:AINT 0 "memory_operand")		;; memory
    (FETCHOP:AINT (match_dup 0)
-     (match_operand:AINT 1 "<fetchop_pred>" ""))	;; operand
-   (match_operand:SI 2 "const_int_operand" "")]		;; model
+     (match_operand:AINT 1 "<fetchop_pred>"))		;; operand
+   (match_operand:SI 2 "const_int_operand")]		;; model
   ""
 {
   rs6000_expand_atomic_op (<CODE>, operands[0], operands[1],
@@ -423,9 +423,9 @@
 })
 
 (define_expand "atomic_nand<mode>"
-  [(match_operand:AINT 0 "memory_operand" "")		;; memory
-   (match_operand:AINT 1 "int_reg_operand" "")		;; operand
-   (match_operand:SI 2 "const_int_operand" "")]		;; model
+  [(match_operand:AINT 0 "memory_operand")		;; memory
+   (match_operand:AINT 1 "int_reg_operand")		;; operand
+   (match_operand:SI 2 "const_int_operand")]		;; model
   ""
 {
   rs6000_expand_atomic_op (NOT, operands[0], operands[1],
@@ -434,11 +434,11 @@
 })
 
 (define_expand "atomic_fetch_<fetchop_name><mode>"
-  [(match_operand:AINT 0 "int_reg_operand" "")		;; output
-   (match_operand:AINT 1 "memory_operand" "")		;; memory
+  [(match_operand:AINT 0 "int_reg_operand")		;; output
+   (match_operand:AINT 1 "memory_operand")		;; memory
    (FETCHOP:AINT (match_dup 1)
-     (match_operand:AINT 2 "<fetchop_pred>" ""))	;; operand
-   (match_operand:SI 3 "const_int_operand" "")]		;; model
+     (match_operand:AINT 2 "<fetchop_pred>"))		;; operand
+   (match_operand:SI 3 "const_int_operand")]		;; model
   ""
 { 
   rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
@@ -447,10 +447,10 @@
 })
 
 (define_expand "atomic_fetch_nand<mode>"
-  [(match_operand:AINT 0 "int_reg_operand" "")		;; output
-   (match_operand:AINT 1 "memory_operand" "")		;; memory
-   (match_operand:AINT 2 "int_reg_operand" "")		;; operand
-   (match_operand:SI 3 "const_int_operand" "")]		;; model
+  [(match_operand:AINT 0 "int_reg_operand")		;; output
+   (match_operand:AINT 1 "memory_operand")		;; memory
+   (match_operand:AINT 2 "int_reg_operand")		;; operand
+   (match_operand:SI 3 "const_int_operand")]		;; model
   ""
 {
   rs6000_expand_atomic_op (NOT, operands[1], operands[2],
@@ -459,11 +459,11 @@
 })
 
 (define_expand "atomic_<fetchop_name>_fetch<mode>"
-  [(match_operand:AINT 0 "int_reg_operand" "")		;; output
-   (match_operand:AINT 1 "memory_operand" "")		;; memory
+  [(match_operand:AINT 0 "int_reg_operand")		;; output
+   (match_operand:AINT 1 "memory_operand")		;; memory
    (FETCHOP:AINT (match_dup 1)
-     (match_operand:AINT 2 "<fetchop_pred>" ""))	;; operand
-   (match_operand:SI 3 "const_int_operand" "")]		;; model
+     (match_operand:AINT 2 "<fetchop_pred>"))		;; operand
+   (match_operand:SI 3 "const_int_operand")]		;; model
   ""
 {
   rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
@@ -472,10 +472,10 @@
 })
 
 (define_expand "atomic_nand_fetch<mode>"
-  [(match_operand:AINT 0 "int_reg_operand" "")		;; output
-   (match_operand:AINT 1 "memory_operand" "")		;; memory
-   (match_operand:AINT 2 "int_reg_operand" "")		;; operand
-   (match_operand:SI 3 "const_int_operand" "")]		;; model
+  [(match_operand:AINT 0 "int_reg_operand")		;; output
+   (match_operand:AINT 1 "memory_operand")		;; memory
+   (match_operand:AINT 2 "int_reg_operand")		;; operand
+   (match_operand:SI 3 "const_int_operand")]		;; model
   ""
 {
   rs6000_expand_atomic_op (NOT, operands[1], operands[2],