Skip to content

R
riscv-gcc-1
Commit acfab996 by Aldy Hernandez Committed by Aldy Hernandez
Options

rs6000.md (altivec_stvx): Add parallels to stvx. 


        * config/rs6000/rs6000.md (altivec_stvx): Add parallels to stvx.
        (altivec_lvsl): Change constraint to b.
        (altivec_lvsr): Same.
        (altivec_lvebx): Same.
        (altivec_lvehx): Same.
        (altivec_lvewx): Same.
        (altivec_lvxl): Same.
        (altivec_lvx): Same.
        (altivec_stvx): Add parallel.
        (altivec_stvxl): Same.
        (altivec_stvehx): Same.
        (altivec_stvebx): Same.
        (altivec_stvebx): Same.

From-SVN: r48890
parent 33b16473
Showing with 51 additions and 26 deletions
gcc/ChangeLog
2002-01-15 Aldy Hernandez <aldyh@redhat.com> 2002-01-15 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md (altivec_stvx): Add parallels to stvx.
(altivec_lvsl): Change constraint to b.
(altivec_lvsr): Same.
(altivec_lvebx): Same.
(altivec_lvehx): Same.
(altivec_lvewx): Same.
(altivec_lvxl): Same.
(altivec_lvx): Same.
(altivec_stvx): Add parallel.
(altivec_stvxl): Same.
(altivec_stvehx): Same.
(altivec_stvebx): Same.
(altivec_stvebx): Same.
2002-01-15 Aldy Hernandez <aldyh@redhat.com>
* config.gcc: Change altivec.h to altivec-defs.h. * config.gcc: Change altivec.h to altivec-defs.h.
* config/rs6000/altivec.h: Delete. * config/rs6000/altivec.h: Delete.
......
gcc/config/rs6000/rs6000.md
...@@ -15496,7 +15496,7 @@ ...@@ -15496,7 +15496,7 @@
(define_insn "altivec_lvsl" (define_insn "altivec_lvsl"
[(set (match_operand:V16QI 0 "register_operand" "=v") [(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "r") (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 194))] (match_operand:SI 2 "register_operand" "r")] 194))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"lvsl %0,%1,%2" "lvsl %0,%1,%2"
...@@ -15504,7 +15504,7 @@ ...@@ -15504,7 +15504,7 @@
(define_insn "altivec_lvsr" (define_insn "altivec_lvsr"
[(set (match_operand:V16QI 0 "register_operand" "=v") [(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "r") (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 195))] (match_operand:SI 2 "register_operand" "r")] 195))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"lvsr %0,%1,%2" "lvsr %0,%1,%2"
...@@ -15512,7 +15512,7 @@ ...@@ -15512,7 +15512,7 @@
(define_insn "altivec_lvebx" (define_insn "altivec_lvebx"
[(set (match_operand:V16QI 0 "register_operand" "=v") [(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:SI 1 "register_operand" "r") (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 196))] (match_operand:SI 2 "register_operand" "r")] 196))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"lvebx %0,%1,%2" "lvebx %0,%1,%2"
...@@ -15520,7 +15520,7 @@ ...@@ -15520,7 +15520,7 @@
(define_insn "altivec_lvehx" (define_insn "altivec_lvehx"
[(set (match_operand:V8HI 0 "register_operand" "=v") [(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:SI 1 "register_operand" "r") (unspec:V8HI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 197))] (match_operand:SI 2 "register_operand" "r")] 197))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"lvehx %0,%1,%2" "lvehx %0,%1,%2"
...@@ -15528,7 +15528,7 @@ ...@@ -15528,7 +15528,7 @@
(define_insn "altivec_lvewx" (define_insn "altivec_lvewx"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "r") (unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 198))] (match_operand:SI 2 "register_operand" "r")] 198))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"lvewx %0,%1,%2" "lvewx %0,%1,%2"
...@@ -15536,7 +15536,7 @@ ...@@ -15536,7 +15536,7 @@
(define_insn "altivec_lvxl" (define_insn "altivec_lvxl"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "r") (unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 199))] (match_operand:SI 2 "register_operand" "r")] 199))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"lvxl %0,%1,%2" "lvxl %0,%1,%2"
...@@ -15544,18 +15544,23 @@ ...@@ -15544,18 +15544,23 @@
(define_insn "altivec_lvx" (define_insn "altivec_lvx"
[(set (match_operand:V4SI 0 "register_operand" "=v") [(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:SI 1 "register_operand" "r") (unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 200))] (match_operand:SI 2 "register_operand" "r")] 200))]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"lvx %0,%1,%2" "lvx %0,%1,%2"
[(set_attr "type" "vecload")]) [(set_attr "type" "vecload")])
;; Parallel the STV*'s with unspecs because some of them have
;; identical rtl but are different instructions-- and gcc gets confused.
(define_insn "altivec_stvx" (define_insn "altivec_stvx"
[(set (mem:V4SI [(parallel
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "r") [(set (mem:V4SI
(match_operand:SI 1 "register_operand" "r")) (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(const_int -16))) (match_operand:SI 1 "register_operand" "r"))
(match_operand:V4SI 2 "register_operand" "v"))] (const_int -16)))
(match_operand:V4SI 2 "register_operand" "v"))
(unspec [(const_int 0)] 201)])]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"stvx %2,%0,%1" "stvx %2,%0,%1"
[(set_attr "type" "vecstore")]) [(set_attr "type" "vecstore")])
...@@ -15563,11 +15568,11 @@ ...@@ -15563,11 +15568,11 @@
(define_insn "altivec_stvxl" (define_insn "altivec_stvxl"
[(parallel [(parallel
[(set (mem:V4SI [(set (mem:V4SI
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "r") (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r")) (match_operand:SI 1 "register_operand" "r"))
(const_int -16))) (const_int -16)))
(match_operand:V4SI 2 "register_operand" "v")) (match_operand:V4SI 2 "register_operand" "v"))
(unspec [(const_int 0)] 201)])] (unspec [(const_int 0)] 202)])]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"stvxl %2,%0,%1" "stvxl %2,%0,%1"
[(set_attr "type" "vecstore")]) [(set_attr "type" "vecstore")])
...@@ -15575,30 +15580,34 @@ ...@@ -15575,30 +15580,34 @@
(define_insn "altivec_stvebx" (define_insn "altivec_stvebx"
[(parallel [(parallel
[(set (mem:V16QI [(set (mem:V16QI
(plus:SI (match_operand:SI 0 "register_operand" "r") (plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r"))) (match_operand:SI 1 "register_operand" "r")))
(match_operand:V16QI 2 "register_operand" "v")) (match_operand:V16QI 2 "register_operand" "v"))
(unspec [(const_int 0)] 202)])] (unspec [(const_int 0)] 203)])]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"stvebx %2,%0,%1" "stvebx %2,%0,%1"
[(set_attr "type" "vecstore")]) [(set_attr "type" "vecstore")])
(define_insn "altivec_stvehx" (define_insn "altivec_stvehx"
[(set (mem:V8HI [(parallel
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "r") [(set (mem:V8HI
(match_operand:SI 1 "register_operand" "r")) (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(const_int -2))) (match_operand:SI 1 "register_operand" "r"))
(match_operand:V8HI 2 "register_operand" "v"))] (const_int -2)))
(match_operand:V8HI 2 "register_operand" "v"))
(unspec [(const_int 0)] 204)])]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"stvehx %2,%0,%1" "stvehx %2,%0,%1"
[(set_attr "type" "vecstore")]) [(set_attr "type" "vecstore")])
(define_insn "altivec_stvewx" (define_insn "altivec_stvewx"
[(set (mem:V4SI [(parallel
(and:SI (plus:SI (match_operand:SI 0 "register_operand" "r") [(set (mem:V4SI
(match_operand:SI 1 "register_operand" "r")) (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(const_int -4))) (match_operand:SI 1 "register_operand" "r"))
(match_operand:V4SI 2 "register_operand" "v"))] (const_int -4)))
(match_operand:V4SI 2 "register_operand" "v"))
(unspec [(const_int 0)] 205)])]
"TARGET_ALTIVEC" "TARGET_ALTIVEC"
"stvewx %2,%0,%1" "stvewx %2,%0,%1"
[(set_attr "type" "vecstore")]) [(set_attr "type" "vecstore")])
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment