Commit accbd151 by Paolo Bonzini Committed by Paolo Bonzini

arm.c (arm_final_prescan_ins): Eliminate code related to jump_clobbers.

2009-06-28  Paolo Bonzini  <bonzini@gnu.org>

        * config/arm/arm.c (arm_final_prescan_ins): Eliminate code
        related to jump_clobbers.
        * config/arm/arm.md (conds): Remove jump_clob case.
        (addsi3_cbranch, addsi3_cbranch_scratch, subsi3_cbranch, two
        splits): Change comparison_operator to arm_comparison_operator.
        (*arm_buneq, *arm_bltgt, *arm_buneq_reversed, *arm_bltgt_reversed):
        Eliminate.

From-SVN: r149034
parent 45475a3f
2009-06-28 Paolo Bonzini <bonzini@gnu.org> 2009-06-28 Paolo Bonzini <bonzini@gnu.org>
* config/arm/arm.c (arm_final_prescan_ins): Eliminate code
related to jump_clobbers.
* config/arm/arm.md (conds): Remove jump_clob case.
(addsi3_cbranch, addsi3_cbranch_scratch, subsi3_cbranch, two
splits): Change comparison_operator to arm_comparison_operator.
(*arm_buneq, *arm_bltgt, *arm_buneq_reversed, *arm_bltgt_reversed):
Eliminate.
2009-06-28 Paolo Bonzini <bonzini@gnu.org>
* dojump.c (do_compare_rtx_and_jump): Try swapping the * dojump.c (do_compare_rtx_and_jump): Try swapping the
condition for floating point modes. condition for floating point modes.
* expmed.c (emit_store_flag_1): Move here a bigger part * expmed.c (emit_store_flag_1): Move here a bigger part
......
...@@ -14487,12 +14487,6 @@ arm_final_prescan_insn (rtx insn) ...@@ -14487,12 +14487,6 @@ arm_final_prescan_insn (rtx insn)
reversed if it appears to fail. */ reversed if it appears to fail. */
int reverse = 0; int reverse = 0;
/* JUMP_CLOBBERS will be one implies that the conditions if a branch is
taken are clobbered, even if the rtl suggests otherwise. It also
means that we have to grub around within the jump expression to find
out what the conditions are when the jump isn't taken. */
int jump_clobbers = 0;
/* If we start with a return insn, we only succeed if we find another one. */ /* If we start with a return insn, we only succeed if we find another one. */
int seeking_return = 0; int seeking_return = 0;
...@@ -14571,14 +14565,6 @@ arm_final_prescan_insn (rtx insn) ...@@ -14571,14 +14565,6 @@ arm_final_prescan_insn (rtx insn)
int then_not_else = TRUE; int then_not_else = TRUE;
rtx this_insn = start_insn, label = 0; rtx this_insn = start_insn, label = 0;
/* If the jump cannot be done with one instruction, we cannot
conditionally execute the instruction in the inverse case. */
if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
{
jump_clobbers = 1;
return;
}
/* Register the insn jumped to. */ /* Register the insn jumped to. */
if (reverse) if (reverse)
{ {
...@@ -14621,13 +14607,7 @@ arm_final_prescan_insn (rtx insn) ...@@ -14621,13 +14607,7 @@ arm_final_prescan_insn (rtx insn)
control falls in from somewhere else. */ control falls in from somewhere else. */
if (this_insn == label) if (this_insn == label)
{ {
if (jump_clobbers) arm_ccfsm_state = 1;
{
arm_ccfsm_state = 2;
this_insn = next_nonnote_insn (this_insn);
}
else
arm_ccfsm_state = 1;
succeed = TRUE; succeed = TRUE;
} }
else else
...@@ -14642,13 +14622,7 @@ arm_final_prescan_insn (rtx insn) ...@@ -14642,13 +14622,7 @@ arm_final_prescan_insn (rtx insn)
this_insn = next_nonnote_insn (this_insn); this_insn = next_nonnote_insn (this_insn);
if (this_insn && this_insn == label) if (this_insn && this_insn == label)
{ {
if (jump_clobbers) arm_ccfsm_state = 1;
{
arm_ccfsm_state = 2;
this_insn = next_nonnote_insn (this_insn);
}
else
arm_ccfsm_state = 1;
succeed = TRUE; succeed = TRUE;
} }
else else
...@@ -14676,13 +14650,7 @@ arm_final_prescan_insn (rtx insn) ...@@ -14676,13 +14650,7 @@ arm_final_prescan_insn (rtx insn)
if (this_insn && this_insn == label if (this_insn && this_insn == label
&& insns_skipped < max_insns_skipped) && insns_skipped < max_insns_skipped)
{ {
if (jump_clobbers) arm_ccfsm_state = 1;
{
arm_ccfsm_state = 2;
this_insn = next_nonnote_insn (this_insn);
}
else
arm_ccfsm_state = 1;
succeed = TRUE; succeed = TRUE;
} }
else else
...@@ -14788,25 +14756,11 @@ arm_final_prescan_insn (rtx insn) ...@@ -14788,25 +14756,11 @@ arm_final_prescan_insn (rtx insn)
} }
arm_target_insn = this_insn; arm_target_insn = this_insn;
} }
if (jump_clobbers)
{ /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
gcc_assert (!reverse); what it was. */
arm_current_cc = if (!reverse)
get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 0));
0), 0), 1));
if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
}
else
{
/* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
what it was. */
if (!reverse)
arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
0));
}
if (reverse || then_not_else) if (reverse || then_not_else)
arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
......
...@@ -334,15 +334,12 @@ ...@@ -334,15 +334,12 @@
; CLOB means that the condition codes are altered in an undefined manner, if ; CLOB means that the condition codes are altered in an undefined manner, if
; they are altered at all ; they are altered at all
; ;
; JUMP_CLOB is used when the condition cannot be represented by a single
; instruction (UNEQ and LTGT). These cannot be predicated.
;
; UNCONDITIONAL means the instions can not be conditionally executed. ; UNCONDITIONAL means the instions can not be conditionally executed.
; ;
; NOCOND means that the condition codes are neither altered nor affect the ; NOCOND means that the condition codes are neither altered nor affect the
; output of this insn ; output of this insn
(define_attr "conds" "use,set,clob,jump_clob,unconditional,nocond" (define_attr "conds" "use,set,clob,unconditional,nocond"
(if_then_else (eq_attr "type" "call") (if_then_else (eq_attr "type" "call")
(const_string "clob") (const_string "clob")
(if_then_else (eq_attr "neon_type" "none") (if_then_else (eq_attr "neon_type" "none")
...@@ -7420,7 +7417,7 @@ ...@@ -7420,7 +7417,7 @@
(define_insn "*addsi3_cbranch" (define_insn "*addsi3_cbranch"
[(set (pc) [(set (pc)
(if_then_else (if_then_else
(match_operator 4 "comparison_operator" (match_operator 4 "arm_comparison_operator"
[(plus:SI [(plus:SI
(match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1") (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1")
(match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ")) (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ"))
...@@ -7502,7 +7499,7 @@ ...@@ -7502,7 +7499,7 @@
(define_insn "*addsi3_cbranch_scratch" (define_insn "*addsi3_cbranch_scratch"
[(set (pc) [(set (pc)
(if_then_else (if_then_else
(match_operator 3 "comparison_operator" (match_operator 3 "arm_comparison_operator"
[(plus:SI [(plus:SI
(match_operand:SI 1 "s_register_operand" "%l,l,l,0") (match_operand:SI 1 "s_register_operand" "%l,l,l,0")
(match_operand:SI 2 "reg_or_int_operand" "J,l,L,IJ")) (match_operand:SI 2 "reg_or_int_operand" "J,l,L,IJ"))
...@@ -7570,7 +7567,7 @@ ...@@ -7570,7 +7567,7 @@
(define_insn "*subsi3_cbranch" (define_insn "*subsi3_cbranch"
[(set (pc) [(set (pc)
(if_then_else (if_then_else
(match_operator 4 "comparison_operator" (match_operator 4 "arm_comparison_operator"
[(minus:SI [(minus:SI
(match_operand:SI 2 "s_register_operand" "l,l,1,l") (match_operand:SI 2 "s_register_operand" "l,l,1,l")
(match_operand:SI 3 "s_register_operand" "l,l,l,l")) (match_operand:SI 3 "s_register_operand" "l,l,l,l"))
...@@ -7811,38 +7808,6 @@ ...@@ -7811,38 +7808,6 @@
;; Patterns to match conditional branch insns. ;; Patterns to match conditional branch insns.
;; ;;
; Special pattern to match UNEQ.
(define_insn "*arm_buneq"
[(set (pc)
(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"*
gcc_assert (!arm_ccfsm_state);
return \"bvs\\t%l0\;beq\\t%l0\";
"
[(set_attr "conds" "jump_clob")
(set_attr "length" "8")]
)
; Special pattern to match LTGT.
(define_insn "*arm_bltgt"
[(set (pc)
(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"*
gcc_assert (!arm_ccfsm_state);
return \"bmi\\t%l0\;bgt\\t%l0\";
"
[(set_attr "conds" "jump_clob")
(set_attr "length" "8")]
)
(define_insn "*arm_cond_branch" (define_insn "*arm_cond_branch"
[(set (pc) [(set (pc)
(if_then_else (match_operator 1 "arm_comparison_operator" (if_then_else (match_operator 1 "arm_comparison_operator"
...@@ -7862,38 +7827,6 @@ ...@@ -7862,38 +7827,6 @@
(set_attr "type" "branch")] (set_attr "type" "branch")]
) )
; Special pattern to match reversed UNEQ.
(define_insn "*arm_buneq_reversed"
[(set (pc)
(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))]
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"*
gcc_assert (!arm_ccfsm_state);
return \"bmi\\t%l0\;bgt\\t%l0\";
"
[(set_attr "conds" "jump_clob")
(set_attr "length" "8")]
)
; Special pattern to match reversed LTGT.
(define_insn "*arm_bltgt_reversed"
[(set (pc)
(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))]
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"*
gcc_assert (!arm_ccfsm_state);
return \"bvs\\t%l0\;beq\\t%l0\";
"
[(set_attr "conds" "jump_clob")
(set_attr "length" "8")]
)
(define_insn "*arm_cond_branch_reversed" (define_insn "*arm_cond_branch_reversed"
[(set (pc) [(set (pc)
(if_then_else (match_operator 1 "arm_comparison_operator" (if_then_else (match_operator 1 "arm_comparison_operator"
...@@ -9600,7 +9533,7 @@ ...@@ -9600,7 +9533,7 @@
(compare:CC_NOOV (ior:SI (compare:CC_NOOV (ior:SI
(and:SI (match_operand:SI 0 "s_register_operand" "") (and:SI (match_operand:SI 0 "s_register_operand" "")
(const_int 1)) (const_int 1))
(match_operator:SI 1 "comparison_operator" (match_operator:SI 1 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand" "") [(match_operand:SI 2 "s_register_operand" "")
(match_operand:SI 3 "arm_add_operand" "")])) (match_operand:SI 3 "arm_add_operand" "")]))
(const_int 0))) (const_int 0)))
...@@ -9617,7 +9550,7 @@ ...@@ -9617,7 +9550,7 @@
(define_split (define_split
[(set (reg:CC_NOOV CC_REGNUM) [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (ior:SI (compare:CC_NOOV (ior:SI
(match_operator:SI 1 "comparison_operator" (match_operator:SI 1 "arm_comparison_operator"
[(match_operand:SI 2 "s_register_operand" "") [(match_operand:SI 2 "s_register_operand" "")
(match_operand:SI 3 "arm_add_operand" "")]) (match_operand:SI 3 "arm_add_operand" "")])
(and:SI (match_operand:SI 0 "s_register_operand" "") (and:SI (match_operand:SI 0 "s_register_operand" "")
......
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