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lvzhengyang
riscv-gcc-1
Commits
abf80f8f
Commit
abf80f8f
authored
Dec 14, 2001
by
Jan Hubicka
Committed by
Jan Hubicka
Dec 14, 2001
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* i386.md (sqrt?f): Fix conditionals.
From-SVN: r48003
parent
938f3777
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gcc/ChangeLog
+4
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gcc/config/i386/i386.md
+6
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gcc/ChangeLog
View file @
abf80f8f
Fri
Dec
14
19
:
53
:
23
CET
2001
Jan
Hubicka
<
jh
@suse
.
cz
>
*
i386
.
md
(
sqrt
?
f
):
Fix
conditionals
.
Fri
Dec
14
07
:
29
:
52
2001
Douglas
B
.
Rupp
<
rupp
@gnat
.
com
>
Fri
Dec
14
07
:
29
:
52
2001
Douglas
B
.
Rupp
<
rupp
@gnat
.
com
>
*
config
.
gcc
(
alpha64
-
dec
-*
vms
*
)
:
New
case
.
*
config
.
gcc
(
alpha64
-
dec
-*
vms
*
)
:
New
case
.
...
...
gcc/config/i386/i386.md
View file @
abf80f8f
...
@@ -14446,9 +14446,9 @@
...
@@ -14446,9 +14446,9 @@
(define_expand "sqrtsf2"
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "")
[(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
"(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
"(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE
_MATH
"
{
{
if (!TARGET_SSE)
if (!TARGET_SSE
_MATH
)
operands[1] = force_reg (SFmode, operands[1]);
operands[1] = force_reg (SFmode, operands[1]);
})
})
...
@@ -14456,7 +14456,7 @@
...
@@ -14456,7 +14456,7 @@
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& (TARGET_SSE && TARGET_MIX_SSE_I387)"
&& (TARGET_SSE
_MATH
&& TARGET_MIX_SSE_I387)"
"@
"@
fsqrt
fsqrt
sqrtss\t{%1, %0|%0, %1}"
sqrtss\t{%1, %0|%0, %1}"
...
@@ -14467,7 +14467,7 @@
...
@@ -14467,7 +14467,7 @@
(define_insn "sqrtsf2_1_sse_only"
(define_insn "sqrtsf2_1_sse_only"
[(set (match_operand:SF 0 "register_operand" "=x")
[(set (match_operand:SF 0 "register_operand" "=x")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
"TARGET_SSE
_MATH
&& (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
"sqrtss\t{%1, %0|%0, %1}"
"sqrtss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
[(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "mode" "SF")
...
@@ -14477,7 +14477,7 @@
...
@@ -14477,7 +14477,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&&
(!TARGET_SSE && !TARGET_MIX_SSE_I387)
"
&&
!TARGET_SSE_MATH
"
"fsqrt"
"fsqrt"
[(set_attr "type" "fpspc")
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")
(set_attr "mode" "SF")
...
@@ -14518,7 +14518,7 @@
...
@@ -14518,7 +14518,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& (!TARGET_SSE2
&& TARGET_SSE_MATH && !TARGET_MIX_SSE_I387
)"
&& (!TARGET_SSE2
|| !TARGET_SSE_MATH
)"
"fsqrt"
"fsqrt"
[(set_attr "type" "fpspc")
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
(set_attr "mode" "DF")
...
...
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