[ARM][1/2] Implement lceil, lfloor, lround optabs with new ARMv8-A instructions.

                                                                                                                                                                             
      PR target/62275
      * config/arm/iterators.md (FIXUORS): New code iterator.
      (VCVT): New int iterator.
      (su_optab): New code attribute.
      (su): Likewise.
      * config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): New pattern.

      PR target/62275
      * gcc.target/arm/lceil-vcvt_1.c: New test.
      * gcc.target/arm/lfloor-vcvt_1.c: Likewise.
      * gcc.target/arm/lround-vcvt_1.c: Likewise.

From-SVN: r214825

gcc/ChangeLog

 2014-09-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
+	PR target/62275
+	* config/arm/iterators.md (FIXUORS): New code iterator.
+	(VCVT): New int iterator.
+	(su_optab): New code attribute.
+	(su): Likewise.
+	* config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): New pattern.
+
+2014-09-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
 	* config/aarch64/predicates.md (aarch64_comparison_operation):
 	New special predicate.
 	* config/aarch64/aarch64.md (*csinc2<mode>_insn): Use

gcc/config/arm/iterators.md

@@ -194,6 +194,9 @@
 ;; Right shifts
 (define_code_iterator rshifts [ashiftrt lshiftrt])
 
+;; Iterator for integer conversions
+(define_code_iterator FIXUORS [fix unsigned_fix])
+
 ;; Binary operators whose second operand can be shifted.
 (define_code_iterator shiftable_ops [plus minus ior xor and])
 
@@ -215,6 +218,8 @@
 (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
                             UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
 
+(define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA])
+
 (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
                               UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN])
 
@@ -519,6 +524,13 @@
 ;; Assembler mnemonics for signedness of widening operations.
 (define_code_attr US [(sign_extend "s") (zero_extend "u")])
 
+;; Signedness suffix for float->fixed conversions.  Empty for signed
+;; conversion.
+(define_code_attr su_optab [(fix "") (unsigned_fix "u")])
+
+;; Sign prefix to use in instruction type suffixes, i.e. s32, u32.
+(define_code_attr su [(fix "s") (unsigned_fix "u")])
+
 ;; Right shifts
 (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
 (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])

gcc/config/arm/vfp.md

@@ -1303,6 +1303,18 @@
    (set_attr "conds" "<vrint_conds>")]
 )
 
+;; Implements the lround, lfloor and lceil optabs.
+(define_insn "l<vrint_pattern><su_optab><mode>si2"
+  [(set (match_operand:SI 0 "register_operand" "=t")
+        (FIXUORS:SI (unspec:SDF
+                        [(match_operand:SDF 1
+                           "register_operand" "<F_constraint>")] VCVT)))]
+  "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+  "vcvt<vrint_variant>%?.<su>32.<V_if_elem>\\t%0, %<V_reg>1"
+  [(set_attr "predicable" "no")
+   (set_attr "type" "f_cvtf2i")]
+)
+
 ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
 ;; The 'smax' and 'smin' RTL standard pattern names do not specify which
 ;; operand will be returned when both operands are zero (i.e. they may not

gcc/testsuite/ChangeLog

+2014-09-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/62275
+	* gcc.target/arm/lceil-vcvt_1.c: New test.
+	* gcc.target/arm/lfloor-vcvt_1.c: Likewise.
+	* gcc.target/arm/lround-vcvt_1.c: Likewise.
+
 2014-09-02  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	DR 1453

gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c

+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2 -march=armv8-a" } */
+/* { dg-add-options arm_v8_vfp } */
+
+int
+foofloat (float x)
+{
+  return __builtin_lceilf (x);
+}
+
+/* { dg-final { scan-assembler-times "vcvtp.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */
+
+
+int
+foodouble (double x)
+{
+  return __builtin_lceil (x);
+}
+
+/* { dg-final { scan-assembler-times "vcvtp.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */

gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c

+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2 -march=armv8-a" } */
+/* { dg-add-options arm_v8_vfp } */
+
+int
+foofloat (float x)
+{
+  return __builtin_lfloorf (x);
+}
+
+/* { dg-final { scan-assembler-times "vcvtm.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */
+
+
+int
+foodouble (double x)
+{
+  return __builtin_lfloor (x);
+}
+
+/* { dg-final { scan-assembler-times "vcvtm.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */

gcc/testsuite/gcc.target/arm/lround-vcvt_1.c

+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2 -march=armv8-a -ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+int
+foofloat (float x)
+{
+  return __builtin_lroundf (x);
+}
+
+/* { dg-final { scan-assembler-times "vcvta.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */
+
+
+int
+foodouble (double x)
+{
+  return __builtin_lround (x);
+}
+
+/* { dg-final { scan-assembler-times "vcvta.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */