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lvzhengyang
riscv-gcc-1
Commits
ab408a86
Commit
ab408a86
authored
Mar 03, 1992
by
James Van Artsdalen
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*** empty log message ***
From-SVN: r381
parent
412dc348
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2 changed files
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10 additions
and
6 deletions
+10
-6
gcc/config/i386/i386.c
+1
-1
gcc/config/i386/i386.h
+9
-5
No files found.
gcc/config/i386/i386.c
View file @
ab408a86
...
@@ -49,7 +49,7 @@ static char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
...
@@ -49,7 +49,7 @@ static char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
enum
reg_class
regclass_map
[
FIRST_PSEUDO_REGISTER
]
=
enum
reg_class
regclass_map
[
FIRST_PSEUDO_REGISTER
]
=
{
{
/* ax, dx, cx, bx */
/* ax, dx, cx, bx */
AREG
,
DREG
,
CREG
,
Q_REGS
,
AREG
,
DREG
,
CREG
,
BREG
,
/* si, di, bp, sp */
/* si, di, bp, sp */
SIREG
,
DIREG
,
INDEX_REGS
,
GENERAL_REGS
,
SIREG
,
DIREG
,
INDEX_REGS
,
GENERAL_REGS
,
/* FP registers */
/* FP registers */
...
...
gcc/config/i386/i386.h
View file @
ab408a86
...
@@ -309,13 +309,16 @@ extern int target_flags;
...
@@ -309,13 +309,16 @@ extern int target_flags;
in a smaller-numbered class.
in a smaller-numbered class.
For any two classes, it is very desirable that there be another
For any two classes, it is very desirable that there be another
class that represents their union. */
class that represents their union.
It might seem that class BREG is unnecessary, since no useful 386
opcode needs reg %ebx. But some systems pass args to the OS in ebx,
and the "b" register constraint is useful in asms for syscalls. */
enum
reg_class
enum
reg_class
{
{
NO_REGS
,
NO_REGS
,
AREG
,
DREG
,
CREG
,
AREG
,
DREG
,
CREG
,
BREG
,
Q_REGS
,
/* %eax %ebx %ecx %edx */
Q_REGS
,
/* %eax %ebx %ecx %edx */
SIREG
,
DIREG
,
SIREG
,
DIREG
,
INDEX_REGS
,
/* %eax %ebx %ecx %edx %esi %edi %ebp */
INDEX_REGS
,
/* %eax %ebx %ecx %edx %esi %edi %ebp */
...
@@ -331,7 +334,7 @@ enum reg_class
...
@@ -331,7 +334,7 @@ enum reg_class
#define REG_CLASS_NAMES \
#define REG_CLASS_NAMES \
{ "NO_REGS", \
{ "NO_REGS", \
"AREG", "DREG", "CREG",
\
"AREG", "DREG", "CREG",
"BREG",
\
"Q_REGS", \
"Q_REGS", \
"SIREG", "DIREG", \
"SIREG", "DIREG", \
"INDEX_REGS", \
"INDEX_REGS", \
...
@@ -346,7 +349,7 @@ enum reg_class
...
@@ -346,7 +349,7 @@ enum reg_class
#define REG_CLASS_CONTENTS \
#define REG_CLASS_CONTENTS \
{ 0, \
{ 0, \
0x1, 0x2, 0x4,
/* AREG, DREG, CREG */
\
0x1, 0x2, 0x4,
0x8,
/* AREG, DREG, CREG, BREG */
\
0xf,
/* Q_REGS */
\
0xf,
/* Q_REGS */
\
0x10, 0x20,
/* SIREG, DIREG */
\
0x10, 0x20,
/* SIREG, DIREG */
\
0x1007f,
/* INDEX_REGS */
\
0x1007f,
/* INDEX_REGS */
\
...
@@ -409,6 +412,7 @@ extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
...
@@ -409,6 +412,7 @@ extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
(C) == 't' ? FP_TOP_REG : \
(C) == 't' ? FP_TOP_REG : \
(C) == 'u' ? FP_SECOND_REG : \
(C) == 'u' ? FP_SECOND_REG : \
(C) == 'a' ? AREG : \
(C) == 'a' ? AREG : \
(C) == 'b' ? BREG : \
(C) == 'c' ? CREG : \
(C) == 'c' ? CREG : \
(C) == 'd' ? DREG : \
(C) == 'd' ? DREG : \
(C) == 'D' ? DIREG : \
(C) == 'D' ? DIREG : \
...
...
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