mips-cpus.def: Add definition for p5600.

2014-06-05  Jaydeep Patil  <Jaydeep.Patil@imgtec.com>
	    Prachi Godbole  <Prachi.Godbole@imgtec.com>

	* config/mips/mips-cpus.def: Add definition for p5600.  Updated
	mips32r5 entry to use PROCESSOR_P5600.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips-protos.h (mips_fmadd_bypass): Add prototype.
	* config/mips/mips.c (mips_fmadd_bypass): New function.
	(mips_rtx_cost_data): Add costs for p5600.
	(mips_issue_rate): Add support for p5600.
	(mips_multipass_dfa_lookahead): Likewise.
	* config/mips/mips.h (TUNE_P5600): New define.
	(TUNE_MACC_CHAINS): Add TUNE_P5600.
	(MIPS_ISA_LEVEL_SPEC): Map -march=p5600 to -mips32r5.
	* config/mips/mips.md: Include p5600.md.
	(processor): Add p5600.
	* config/mips/p5600.md: New file.

Co-Authored-By: Prachi Godbole <prachi.godbole@imgtec.com>

From-SVN: r211265

gcc/ChangeLog

+2014-06-05  Jaydeep Patil  <Jaydeep.Patil@imgtec.com>
+	    Prachi Godbole  <Prachi.Godbole@imgtec.com>
+
+	* config/mips/mips-cpus.def: Add definition for p5600.  Updated
+	mips32r5 entry to use PROCESSOR_P5600.
+	* config/mips/mips-tables.opt: Regenerate.
+	* config/mips/mips-protos.h (mips_fmadd_bypass): Add prototype.
+	* config/mips/mips.c (mips_fmadd_bypass): New function.
+	(mips_rtx_cost_data): Add costs for p5600.
+	(mips_issue_rate): Add support for p5600.
+	(mips_multipass_dfa_lookahead): Likewise.
+	* config/mips/mips.h (TUNE_P5600): New define.
+	(TUNE_MACC_CHAINS): Add TUNE_P5600.
+	(MIPS_ISA_LEVEL_SPEC): Map -march=p5600 to -mips32r5.
+	* config/mips/mips.md: Include p5600.md.
+	(processor): Add p5600.
+	* config/mips/p5600.md: New file.
+
 2014-06-05  Evgeny Stupachenko  <evstupac@gmail.com>
 
 	* config/i386/sse.md (*ssse3_palignr<mode>_perm): New.

gcc/config/mips/mips-cpus.def

@@ -49,7 +49,7 @@ MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33, PTF_AVOID_BRANCHLIKELY)
    for this yet, so in the short term we will use the same processor entry 
    as mips32r2.  */
 MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY)
-MIPS_CPU ("mips32r5", PROCESSOR_74KF2_1, 36, PTF_AVOID_BRANCHLIKELY)
+MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY)
 MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY)
 /* ??? For now just tune the generic MIPS64r2 and above for 5KC as well.   */
 MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY)
@@ -145,6 +145,9 @@ MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0)
 MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, 33, 0)
 MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0)
 
+/* MIPS32 Release 5 processors.  */
+MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY)
+
 /* MIPS64 processors.  */
 MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0)
 MIPS_CPU ("5kf", PROCESSOR_5KF, 64, 0)

gcc/config/mips/mips-protos.h

@@ -315,6 +315,7 @@ extern bool mips16e_save_restore_pattern_p (rtx, HOST_WIDE_INT,
 extern bool mask_low_and_shift_p (enum machine_mode, rtx, rtx, int);
 extern int mask_low_and_shift_len (enum machine_mode, rtx, rtx);
 extern bool and_operands_ok (enum machine_mode, rtx, rtx);
+extern bool mips_fmadd_bypass (rtx, rtx);
 
 union mips_gen_fn_ptrs
 {

gcc/config/mips/mips-tables.opt

@@ -619,50 +619,53 @@ EnumValue
 Enum(mips_arch_opt_value) String(r1004kf1_1) Value(82)
 
 EnumValue
-Enum(mips_arch_opt_value) String(5kc) Value(83) Canonical
+Enum(mips_arch_opt_value) String(p5600) Value(83) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5kc) Value(83)
+Enum(mips_arch_opt_value) String(5kc) Value(84) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(5kf) Value(84) Canonical
+Enum(mips_arch_opt_value) String(r5kc) Value(84)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5kf) Value(84)
+Enum(mips_arch_opt_value) String(5kf) Value(85) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(20kc) Value(85) Canonical
+Enum(mips_arch_opt_value) String(r5kf) Value(85)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r20kc) Value(85)
+Enum(mips_arch_opt_value) String(20kc) Value(86) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(sb1) Value(86) Canonical
+Enum(mips_arch_opt_value) String(r20kc) Value(86)
 
 EnumValue
-Enum(mips_arch_opt_value) String(sb1a) Value(87) Canonical
+Enum(mips_arch_opt_value) String(sb1) Value(87) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(sr71000) Value(88) Canonical
+Enum(mips_arch_opt_value) String(sb1a) Value(88) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(sr71k) Value(88)
+Enum(mips_arch_opt_value) String(sr71000) Value(89) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(xlr) Value(89) Canonical
+Enum(mips_arch_opt_value) String(sr71k) Value(89)
 
 EnumValue
-Enum(mips_arch_opt_value) String(loongson3a) Value(90) Canonical
+Enum(mips_arch_opt_value) String(xlr) Value(90) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon) Value(91) Canonical
+Enum(mips_arch_opt_value) String(loongson3a) Value(91) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon+) Value(92) Canonical
+Enum(mips_arch_opt_value) String(octeon) Value(92) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon2) Value(93) Canonical
+Enum(mips_arch_opt_value) String(octeon+) Value(93) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(xlp) Value(94) Canonical
+Enum(mips_arch_opt_value) String(octeon2) Value(94) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(xlp) Value(95) Canonical
 

gcc/config/mips/mips.c

@@ -1180,6 +1180,19 @@ static const struct mips_rtx_cost_data
     COSTS_N_INSNS (68),           /* int_div_di */
 		     1,           /* branch_cost */
 		     4            /* memory_latency */
+  },
+  { /* P5600 */
+    COSTS_N_INSNS (4),            /* fp_add */
+    COSTS_N_INSNS (5),            /* fp_mult_sf */
+    COSTS_N_INSNS (5),            /* fp_mult_df */
+    COSTS_N_INSNS (17),           /* fp_div_sf */
+    COSTS_N_INSNS (17),           /* fp_div_df */
+    COSTS_N_INSNS (5),            /* int_mult_si */
+    COSTS_N_INSNS (5),            /* int_mult_di */
+    COSTS_N_INSNS (8),            /* int_div_si */
+    COSTS_N_INSNS (8),            /* int_div_di */
+		    2,            /* branch_cost */
+		   10             /* memory_latency */
   }
 };
 
@@ -13073,6 +13086,31 @@ mips_output_division (const char *division, rtx *operands)
   return s;
 }
 
+/* Return true if destination of IN_INSN is used as add source in
+   OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
+   madd.s dst, x, y, z
+   madd.s a, dst, b, c  */
+
+bool
+mips_fmadd_bypass (rtx out_insn, rtx in_insn)
+{
+  int dst_reg, src_reg;
+  
+  gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
+  gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
+
+  extract_insn (in_insn);
+  dst_reg = REG_P (recog_data.operand[0]);
+
+  extract_insn (out_insn);
+  src_reg = REG_P (recog_data.operand[1]);
+
+  if (dst_reg == src_reg)
+    return true;
+
+  return false;
+}
+
 /* Return true if IN_INSN is a multiply-add or multiply-subtract
    instruction and if OUT_INSN assigns to the accumulator operand.  */
 
@@ -13208,6 +13246,7 @@ mips_issue_rate (void)
     case PROCESSOR_LOONGSON_2E:
     case PROCESSOR_LOONGSON_2F:
     case PROCESSOR_LOONGSON_3A:
+    case PROCESSOR_P5600:
       return 4;
 
     case PROCESSOR_XLP:
@@ -13343,6 +13382,9 @@ mips_multipass_dfa_lookahead (void)
   if (TUNE_OCTEON)
     return 2;
 
+  if (TUNE_P5600)
+    return 4;
+
   return 0;
 }
 

gcc/config/mips/mips.h

@@ -264,6 +264,7 @@ struct mips_cpu_info {
 				     || mips_tune == PROCESSOR_OCTEON2)
 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1		\
 				     || mips_tune == PROCESSOR_SB1A)
+#define TUNE_P5600                  (mips_tune == PROCESSOR_P5600)
 
 /* Whether vector modes and intrinsics for ST Microelectronics
    Loongson-2E/2F processors should be enabled.  In o32 pairs of
@@ -306,7 +307,8 @@ struct mips_cpu_info {
 #define TUNE_MACC_CHAINS	    (TUNE_MIPS5500		\
 				     || TUNE_MIPS4120		\
 				     || TUNE_MIPS4130		\
-				     || TUNE_24K)
+				     || TUNE_24K		\
+				     || TUNE_P5600)
 
 #define TARGET_OLDABI		    (mips_abi == ABI_32 || mips_abi == ABI_O64)
 #define TARGET_NEWABI		    (mips_abi == ABI_N32 || mips_abi == ABI_64)
@@ -724,7 +726,7 @@ struct mips_cpu_info {
      %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
        |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
      %{march=mips32r3: -mips32r3} \
-     %{march=mips32r5: -mips32r5} \
+     %{march=mips32r5|march=p5600: -mips32r5} \
      %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
        |march=xlr: -mips64} \
      %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \

gcc/config/mips/mips.md

@@ -65,6 +65,7 @@
   sr71000
   xlr
   xlp
+  p5600
 ])
 
 (define_c_enum "unspec" [
@@ -1050,6 +1051,7 @@
   (eq_attr "type" "ghost")
   "nothing")
 
+(include "p5600.md")
 (include "4k.md")
 (include "5k.md")
 (include "20kc.md")

gcc/config/mips/p5600.md

+;; DFA-based pipeline description for P5600.
+;;
+;; Copyright (C) 2007-2014 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "p5600_agen_pipe, p5600_alu_pipe, p5600_fpu_pipe")
+
+;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes
+(define_cpu_unit "p5600_agq, p5600_al2, p5600_ctistd, p5600_ldsta,
+		  p5600_gpdiv" "p5600_agen_pipe")
+
+;; The arithmetic-logic-unit queue (ALQ) has ALU pipe
+(define_cpu_unit "p5600_alq, p5600_alu" "p5600_alu_pipe")
+
+;; The floating-point-unit queue (FPQ) has short and long pipes
+(define_cpu_unit "p5600_fpu_short, p5600_fpu_long" "p5600_fpu_pipe")
+
+;; Short FPU pipeline
+(define_cpu_unit "p5600_fpu_store" "p5600_fpu_pipe")
+
+;; Long FPU pipeline
+(define_cpu_unit "p5600_fpu_apu" "p5600_fpu_pipe")
+
+(define_reservation "p5600_agq_al2" "p5600_agq, p5600_al2")
+(define_reservation "p5600_agq_ctistd" "p5600_agq, p5600_ctistd")
+(define_reservation "p5600_agq_ldsta" "p5600_agq, p5600_ldsta")
+(define_reservation "p5600_alq_alu" "p5600_alq, p5600_alu")
+
+;;
+;; FPU pipe
+;;
+
+;; fadd, fsub
+(define_insn_reservation "p5600_fpu_fadd" 4
+  (eq_attr "type" "fadd,fabs,fneg")
+  "p5600_fpu_long, p5600_fpu_apu")
+
+;; fabs, fneg, fcmp
+(define_insn_reservation "p5600_fpu_fabs" 2
+  (eq_attr "type" "fabs,fneg,fcmp,fmove")
+  "p5600_fpu_short, p5600_fpu_apu")
+
+;; fload
+(define_insn_reservation "p5600_fpu_fload" 8
+  (eq_attr "type" "fpload,fpidxload")
+  "p5600_fpu_long, p5600_fpu_apu")
+
+;; fstore
+(define_insn_reservation "p5600_fpu_fstore" 1
+  (eq_attr "type" "fpstore,fpidxstore")
+  "p5600_fpu_short, p5600_fpu_apu")
+
+;; fmadd
+(define_insn_reservation "p5600_fpu_fmadd" 9
+  (eq_attr "type" "fmadd")
+  "p5600_fpu_long, p5600_fpu_apu")
+
+;; fmul
+(define_insn_reservation "p5600_fpu_fmul" 5
+  (eq_attr "type" "fmul")
+  "p5600_fpu_long, p5600_fpu_apu")
+
+;; fdiv, fsqrt
+(define_insn_reservation "p5600_fpu_div" 17
+  (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
+  "p5600_fpu_long, p5600_fpu_apu*17")
+
+;; fcvt
+(define_insn_reservation "p5600_fpu_fcvt" 4
+  (eq_attr "type" "fcvt")
+  "p5600_fpu_long, p5600_fpu_apu")
+
+;; mtc
+(define_insn_reservation "p5600_fpu_fmtc" 7
+  (eq_attr "type" "mtc")
+  "p5600_fpu_short, p5600_fpu_store")
+
+;; mfc
+(define_insn_reservation "p5600_fpu_fmfc" 4
+  (eq_attr "type" "mfc")
+  "p5600_fpu_short, p5600_fpu_store")
+
+;; madd/msub feeding into the add source
+;; madd.fmt dst, x, y, z -> madd.fmt a, dst, b, c 5 cycles
+(define_bypass 5 "p5600_fpu_fmadd" "p5600_fpu_fmadd" "mips_fmadd_bypass")
+
+;;
+;; Integer pipe
+;;
+
+;; and
+(define_insn_reservation "p5600_int_and" 1
+  (eq_attr "move_type" "logical")
+  "p5600_alq_alu")
+
+;; lui
+(define_insn_reservation "p5600_int_lui" 1
+  (eq_attr "move_type" "const")
+  "p5600_alq_alu")
+
+;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs
+(define_insn_reservation "p5600_int_load" 4
+  (eq_attr "move_type" "load")
+  "p5600_agq_ldsta")
+
+;; store
+(define_insn_reservation "p5600_int_store" 3
+  (eq_attr "move_type" "store")
+  "p5600_agq_ldsta")
+
+;; andi, sll, srl, seb, seh
+(define_insn_reservation "p5600_int_arith_1" 1
+  (eq_attr "move_type" "andi,sll0,signext")
+  "p5600_agq_al2 | p5600_alq_alu")
+
+;; addi, addiu, ori, xori, add, addu
+(define_insn_reservation "p5600_int_arith_2" 1
+  (eq_attr "alu_type" "add,or,xor")
+  "p5600_agq_al2 | p5600_alq_alu")
+
+;; nor, sub
+(define_insn_reservation "p5600_int_arith_3" 1
+  (eq_attr "alu_type" "nor,sub")
+  "p5600_alq_alu")
+
+;; srl, sra, rotr, slt, sllv, srlv
+(define_insn_reservation "p5600_int_arith_4" 1
+  (eq_attr "type" "shift,slt,move")
+  "p5600_agq_al2 | p5600_alq_alu")
+
+;; nop
+(define_insn_reservation "p5600_int_nop" 0
+  (eq_attr "type" "nop")
+  "p5600_agq_al2")
+
+;; clo, clz
+(define_insn_reservation "p5600_int_countbits" 1
+  (eq_attr "type" "clz")
+  "p5600_agq_al2")
+
+;; Conditional moves
+(define_insn_reservation "p5600_int_condmove" 1
+  (eq_attr "type" "condmove")
+  "p5600_agq_al2")
+
+;; madd, msub
+(define_insn_reservation "p5600_dsp_mac" 5
+  (eq_attr "type" "imadd")
+  "p5600_agq_al2")
+
+;; mfhi/lo
+(define_insn_reservation "p5600_dsp_mfhilo" 1
+  (eq_attr "type" "mfhi,mflo")
+  "p5600_agq_al2")
+
+;; mthi/lo
+(define_insn_reservation "p5600_dsp_mthilo" 5
+  (eq_attr "type" "mthi,mtlo")
+  "p5600_agq_al2")
+
+;; mult, multu, mul
+(define_insn_reservation "p5600_dsp_mult" 5
+  (eq_attr "type" "imul3,imul")
+  "p5600_agq_al2")
+
+;; branch and jump
+(define_insn_reservation "p5600_int_branch" 1
+  (eq_attr "type" "branch,jump")
+  "p5600_agq_ctistd")
+
+;; prefetch
+(define_insn_reservation "p5600_int_prefetch" 3
+  (eq_attr "type" "prefetch,prefetchx")
+  "p5600_agq_ldsta")
+
+;; divide
+(define_insn_reservation "p5600_int_div" 8
+  (eq_attr "type" "idiv")
+  "p5600_agq_al2+p5600_gpdiv*8")
+
+;; arith
+(define_insn_reservation "p5600_int_arith_5" 2
+  (eq_attr "type" "arith")
+  "p5600_agq_al2")
+
+;; call
+(define_insn_reservation "p5600_int_call" 2
+  (eq_attr "jal" "indirect,direct")
+  "p5600_agq_ctistd")

gcc/doc/invoke.texi

@@ -17209,6 +17209,7 @@ The processor names are:
 @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec},
 @samp{octeon}, @samp{octeon+}, @samp{octeon2},
 @samp{orion},
+@samp{p5600},
 @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
 @samp{r4600}, @samp{r4650}, @samp{r4700}, @samp{r6000}, @samp{r8000},
 @samp{rm7000}, @samp{rm9000},