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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
aa4778b6
Commit
aa4778b6
authored
Mar 29, 1999
by
J"orn Rennecke
Committed by
Joern Rennecke
Mar 29, 1999
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* sh.md (mulsi3): Tag an extra REG_EQUAL note to the middle insn.
From-SVN: r26055
parent
51c2de46
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gcc/ChangeLog
View file @
aa4778b6
Mon
Mar
29
20
:
35
:
49
1999
J
"orn Rennecke <amylaar@cygnus.co.uk>
* sh.md (mulsi3): Tag an extra REG_EQUAL note to the middle insn.
Mon Mar 29 11:50:34 1999 Jerry Quinn <jquinn@nortelnetworks.com>
Mon Mar 29 11:50:34 1999 Jerry Quinn <jquinn@nortelnetworks.com>
* pa.h (HAVE_PRE_INCREMENT): Disable when optimizing for a PA8000
* pa.h (HAVE_PRE_INCREMENT): Disable when optimizing for a PA8000
...
...
gcc/config/sh/sh.md
View file @
aa4778b6
...
@@ -1112,8 +1112,17 @@
...
@@ -1112,8 +1112,17 @@
else
else
{
{
rtx macl = gen_rtx_REG (SImode, MACL_REG);
rtx macl = gen_rtx_REG (SImode, MACL_REG);
rtx giv_insn;
first = emit_insn (gen_mul_l (operands[1], operands[2]));
first = emit_insn (gen_mul_l (operands[1], operands[2]));
emit_insn (gen_movsi_i ((operands[0]), macl));
/* consec_sets_giv can only recognize the first insn that sets a
giv as the giv insn. So we must tag this also with a REG_EQUAL
note. */
giv_insn = emit_insn (gen_movsi_i ((operands[0]), macl));
REG_NOTES (giv_insn)
= gen_rtx_EXPR_LIST (REG_EQUAL,
gen_rtx_MULT (SImode, operands[1], operands[2]),
REG_NOTES (giv_insn));
/* The sequence must end in a no-op move, lest cse puts macl in its
/* The sequence must end in a no-op move, lest cse puts macl in its
tables and does invalid substitutions. */
tables and does invalid substitutions. */
last = emit_insn (gen_movsi_i ((operands[0]), operands[0]));
last = emit_insn (gen_movsi_i ((operands[0]), operands[0]));
...
...
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