re PR target/59290 ([ARM] regression on negdi-2.c (big-endian))

[gcc/]
2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/59290
	* config/arm/arm.md (*zextendsidi_negsi): New pattern.
	* config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly
	for zero_extend case.

[gcc/testsuite/]
2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/59290
	* gcc.target/arm/negdi-2.c: Scan more general register names.

From-SVN: r205394

gcc/ChangeLog

+2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/59290
+	* config/arm/arm.md (*zextendsidi_negsi): New pattern.
+	* config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly
+	for zero_extend case.
+
 2013-11-26   H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR bootstrap/55552

gcc/config/arm/arm.c

@@ -10130,6 +10130,8 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  if (speed_p)
 	    *cost += 2 * extra_cost->alu.shift;
 	}
+      else  /* GET_MODE (XEXP (x, 0)) == SImode.  */
+        *cost = COSTS_N_INSNS (1);
 
       /* Widening beyond 32-bits requires one more insn.  */
       if (mode == DImode)

gcc/config/arm/arm.md

@@ -4718,6 +4718,24 @@
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
   "")
 
+(define_insn_and_split "*zextendsidi_negsi"
+  [(set (match_operand:DI 0 "s_register_operand" "=r")
+        (zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))]
+   "TARGET_32BIT"
+   "#"
+   ""
+   [(set (match_dup 2)
+         (neg:SI (match_dup 1)))
+    (set (match_dup 3)
+         (const_int 0))]
+   {
+      operands[2] = gen_lowpart (SImode, operands[0]);
+      operands[3] = gen_highpart (SImode, operands[0]);
+   }
+ [(set_attr "length" "8")
+  (set_attr "type" "multiple")]
+)
+
 ;; Negate an extended 32-bit value.
 (define_insn_and_split "*negdi_extendsidi"
   [(set (match_operand:DI 0 "s_register_operand" "=l,r")

gcc/testsuite/ChangeLog

+2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/59290
+	* gcc.target/arm/negdi-2.c: Scan more general register names.
+
 2013-11-26  Terry Guo  <terry.guo@arm.com>
 
 	* gcc.target/arm/thumb1-pic-high-reg.c: New case.

gcc/testsuite/gcc.target/arm/negdi-2.c

@@ -11,6 +11,6 @@ Expected output:
 	rsb	r0, r0, #0
 	mov	r1, #0
 */
-/* { dg-final { scan-assembler-times "rsb\\tr0, r0, #0" 1 { target { arm_nothumb } } } } */
-/* { dg-final { scan-assembler-times "negs\\tr0, r0" 1 { target { ! arm_nothumb } } } } */
+/* { dg-final { scan-assembler-times "rsb\\t...?, ...?, #0" 1 { target { arm_nothumb } } } } */
+/* { dg-final { scan-assembler-times "negs\\t...?, ...?" 1 { target { ! arm_nothumb } } } } */
 /* { dg-final { scan-assembler-times "mov" 1 } } */