Commit a7dbb777 by Uros Bizjak Committed by Uros Bizjak

i386.md (*andqi_2_maybe_si): Handle potential partial reg stall on alternative 2.

	* config/i386/i386.md (*andqi_2_maybe_si): Handle potential
	partial reg stall on alternative 2.

From-SVN: r273551
parent 4efd8968
2019-07-17 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*andqi_2_maybe_si): Handle potential
partial reg stall on alternative 2.
2019-07-17 Richard Biener <rguenther@suse.de> 2019-07-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/91178 PR tree-optimization/91178
......
...@@ -8689,7 +8689,7 @@ ...@@ -8689,7 +8689,7 @@
(match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "qmn,qn,n")) (match_operand:QI 2 "general_operand" "qmn,qn,n"))
(const_int 0))) (const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r") (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,r")
(and:QI (match_dup 1) (match_dup 2)))] (and:QI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (AND, QImode, operands) "ix86_binary_operator_ok (AND, QImode, operands)
&& ix86_match_ccmode (insn, && ix86_match_ccmode (insn,
...@@ -8705,7 +8705,12 @@ ...@@ -8705,7 +8705,12 @@
return "and{b}\t{%2, %0|%0, %2}"; return "and{b}\t{%2, %0|%0, %2}";
} }
[(set_attr "type" "alu") [(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")]) (set_attr "mode" "QI,QI,SI")
;; Potential partial reg stall on alternative 2.
(set (attr "preferred_for_speed")
(cond [(eq_attr "alternative" "2")
(symbol_ref "!TARGET_PARTIAL_REG_STALL")]
(symbol_ref "true")))])
(define_insn "*and<mode>_2" (define_insn "*and<mode>_2"
[(set (reg FLAGS_REG) [(set (reg FLAGS_REG)
......
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