Commit a7a975e1 by Richard Kenner

*** empty log message ***

From-SVN: r791
parent e5f6a288
...@@ -1234,20 +1234,22 @@ struct rt_cargs {int gregs, fregs; }; ...@@ -1234,20 +1234,22 @@ struct rt_cargs {int gregs, fregs; };
#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
case CONST_INT: \ case CONST_INT: \
if ((OUTER_CODE) == IOR && exact_log2 (INTVAL (RTX)) >= 0 \ if ((OUTER_CODE) == IOR && exact_log2 (INTVAL (RTX)) >= 0 \
|| (OUTER_CODE) == AND && exact_log2 (~INTVAL (RTX)) >= 0 \ || (OUTER_CODE) == AND && exact_log2 (~INTVAL (RTX)) >= 0 \
|| (((OUTER_CODE) == PLUS || (OUTER_CODE) == MINUS) \ || (((OUTER_CODE) == PLUS || (OUTER_CODE) == MINUS) \
&& (unsigned int) (INTVAL (RTX) + 15) < 31) \ && (unsigned int) (INTVAL (RTX) + 15) < 31) \
|| ((OUTER_CODE) == SET && (unsigned int) INTVAL (RTX) < 16))\ || ((OUTER_CODE) == SET && (unsigned int) INTVAL (RTX) < 16))\
return 0; \ return 0; \
return ((unsigned)(INTVAL(RTX) + 0x8000) < 0x10000 || (INTVAL (RTX) & 0xffff0000) == 0) ? 0 : COSTS_N_INSNS (2);\ return ((unsigned int) (INTVAL(RTX) + 0x8000) < 0x10000 \
|| (INTVAL (RTX) & 0xffff0000) == 0) ? 0 : COSTS_N_INSNS (2);\
case CONST: \ case CONST: \
case LABEL_REF: \ case LABEL_REF: \
case SYMBOL_REF: \ case SYMBOL_REF: \
if (current_function_operand (RTX, Pmode)) return 0; \ if (current_function_operand (RTX, Pmode)) return 0; \
return COSTS_N_INSNS (2); return COSTS_N_INSNS (2); \
case CONST_DOUBLE: \ case CONST_DOUBLE: \
if ((RTX) == CONST0_RTX (GET_MODE (RTX))) return 2; \ if ((RTX) == CONST0_RTX (GET_MODE (RTX))) return 2; \
return (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT) ? COSTS_N_INSNS (5) : COSTS_N_INSNS (4); return ((GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT) \
? COSTS_N_INSNS (5) : COSTS_N_INSNS (4));
/* Provide the costs of a rtl expression. This is in the body of a /* Provide the costs of a rtl expression. This is in the body of a
switch on CODE. switch on CODE.
......
...@@ -1081,7 +1081,13 @@ ...@@ -1081,7 +1081,13 @@
int start = INTVAL (operands[3]) & 31; int start = INTVAL (operands[3]) & 31;
int size = INTVAL (operands[2]) & 31; int size = INTVAL (operands[2]) & 31;
if ((start < 16 && start + size <= 16) || start >= 16) /* If the bitfield being tested fits in the upper or lower half of a
word, it is possible to use andiu. or andil. to test it. This is
useful because the condition register set-use delay is smaller for
andi[ul]. than for rlinm. This doesn't work when the starting bit
position is 0 because the LT and GT bits may be set wrong. */
if ((start > 0 && start + size <= 16) || start >= 16)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, operands[3] = gen_rtx (CONST_INT, VOIDmode,
((1 << (16 - (start & 15))) ((1 << (16 - (start & 15)))
...@@ -1114,15 +1120,10 @@ ...@@ -1114,15 +1120,10 @@
int start = INTVAL (operands[3]) & 31; int start = INTVAL (operands[3]) & 31;
int size = INTVAL (operands[2]) & 31; int size = INTVAL (operands[2]) & 31;
if ((start < 16 && start + size <= 16) || start >= 16) if (start >= 16 && start + size == 32)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
((1 << (16 - (start & 15))) return \"andil. %0,%1,%3\";
- (1 << (16 - (start & 15) - size))));
if (start < 16)
return \"andiu. %0,%1,%3\";
else
return \"andil. %0,%1,%3\";
} }
if (start + size >= 32) if (start + size >= 32)
......
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