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riscv-gcc-1
Commit a6340be1 by Bernd Schmidt Committed by Bernd Schmidt
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gcc/ 

	From Michael Frysinger  <michael.frysinger@analog.com>
	* config/bfin/bfin.c (bfin_cpus[]): Add 0.1 for bf522, bf523, bf524,
	bf525, bf526, bf527, bf542, bf544, bf547, bf548, and bf549.  Add 0.2
	for bf538.

gcc/testsuite/
	From Mike Frysinger  <michael.frysinger@analog.com>
	* gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0001.
	* gcc.target/bfin/mcpu-bf523.c: Likewise.
	* gcc.target/bfin/mcpu-bf524.c: Likewise.
	* gcc.target/bfin/mcpu-bf525.c: Likewise.
	* gcc.target/bfin/mcpu-bf526.c: Likewise.
	* gcc.target/bfin/mcpu-bf527.c: Likewise.
	* gcc.target/bfin/mcpu-bf542.c: Likewise.
	* gcc.target/bfin/mcpu-bf544.c: Likewise.
	* gcc.target/bfin/mcpu-bf547.c: Likewise.
	* gcc.target/bfin/mcpu-bf548.c: Likewise.
	* gcc.target/bfin/mcpu-bf549.c: Likewise.

From-SVN: r139935
parent aaf40205
Showing with 68 additions and 22 deletions
gcc/ChangeLog
2008-09-03 Bernd Schmidt <bernd.schmidt@analog.com>
From Michael Frysinger <michael.frysinger@analog.com>
* config/bfin/bfin.c (bfin_cpus[]): Add 0.1 for bf522, bf523, bf524,
bf525, bf526, bf527, bf542, bf544, bf547, bf548, and bf549. Add 0.2
for bf538.
2008-09-03 Hari Sandanagobalane <hariharan@picochip.com> 2008-09-03 Hari Sandanagobalane <hariharan@picochip.com>
Add picoChip port. Add picoChip port.
......
gcc/config/bfin/bfin.c
...@@ -114,21 +114,33 @@ struct bfin_cpu ...@@ -114,21 +114,33 @@ struct bfin_cpu
struct bfin_cpu bfin_cpus[] = struct bfin_cpu bfin_cpus[] =
{ {
{"bf522", BFIN_CPU_BF522, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf522", BFIN_CPU_BF522, 0x0000, {"bf522", BFIN_CPU_BF522, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf523", BFIN_CPU_BF523, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf523", BFIN_CPU_BF523, 0x0000, {"bf523", BFIN_CPU_BF523, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf524", BFIN_CPU_BF524, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf524", BFIN_CPU_BF524, 0x0000, {"bf524", BFIN_CPU_BF524, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf525", BFIN_CPU_BF525, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf525", BFIN_CPU_BF525, 0x0000, {"bf525", BFIN_CPU_BF525, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf526", BFIN_CPU_BF526, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf526", BFIN_CPU_BF526, 0x0000, {"bf526", BFIN_CPU_BF526, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf527", BFIN_CPU_BF527, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf527", BFIN_CPU_BF527, 0x0000, {"bf527", BFIN_CPU_BF527, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
...@@ -178,6 +190,8 @@ struct bfin_cpu bfin_cpus[] = ...@@ -178,6 +190,8 @@ struct bfin_cpu bfin_cpus[] =
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf538", BFIN_CPU_BF538, 0x0003, {"bf538", BFIN_CPU_BF538, 0x0003,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf538", BFIN_CPU_BF538, 0x0002,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf539", BFIN_CPU_BF539, 0x0004, {"bf539", BFIN_CPU_BF539, 0x0004,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
...@@ -186,18 +200,28 @@ struct bfin_cpu bfin_cpus[] = ...@@ -186,18 +200,28 @@ struct bfin_cpu bfin_cpus[] =
{"bf539", BFIN_CPU_BF539, 0x0002, {"bf539", BFIN_CPU_BF539, 0x0002,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf542", BFIN_CPU_BF542, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf542", BFIN_CPU_BF542, 0x0000, {"bf542", BFIN_CPU_BF542, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf544", BFIN_CPU_BF544, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf544", BFIN_CPU_BF544, 0x0000, {"bf544", BFIN_CPU_BF544, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf547", BFIN_CPU_BF547, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf547", BFIN_CPU_BF547, 0x0000, {"bf547", BFIN_CPU_BF547, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf548", BFIN_CPU_BF548, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf548", BFIN_CPU_BF548, 0x0000, {"bf548", BFIN_CPU_BF548, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
{"bf549", BFIN_CPU_BF549, 0x0001,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf549", BFIN_CPU_BF549, 0x0000, {"bf549", BFIN_CPU_BF549, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS}, WA_SPECULATIVE_LOADS | WA_RETS},
......
gcc/testsuite/ChangeLog
2008-09-03 Bernd Schmidt <bernd.schmidt@analog.com>
From Mike Frysinger <michael.frysinger@analog.com>
* gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0001.
* gcc.target/bfin/mcpu-bf523.c: Likewise.
* gcc.target/bfin/mcpu-bf524.c: Likewise.
* gcc.target/bfin/mcpu-bf525.c: Likewise.
* gcc.target/bfin/mcpu-bf526.c: Likewise.
* gcc.target/bfin/mcpu-bf527.c: Likewise.
* gcc.target/bfin/mcpu-bf542.c: Likewise.
* gcc.target/bfin/mcpu-bf544.c: Likewise.
* gcc.target/bfin/mcpu-bf547.c: Likewise.
* gcc.target/bfin/mcpu-bf548.c: Likewise.
* gcc.target/bfin/mcpu-bf549.c: Likewise.
2008-09-02 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2008-09-02 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* gcc.c-torture/compile/pr33009.c: xfail on hppa*-*-*. * gcc.c-torture/compile/pr33009.c: xfail on hppa*-*-*.
......
gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF52x__ is not defined" #error "__ADSPBF52x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF52x__ is not defined" #error "__ADSPBF52x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF52x__ is not defined" #error "__ADSPBF52x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF52x__ is not defined" #error "__ADSPBF52x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF52x__ is not defined" #error "__ADSPBF52x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF52x__ is not defined" #error "__ADSPBF52x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF54x__ is not defined" #error "__ADSPBF54x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF54x__ is not defined" #error "__ADSPBF54x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF54x__ is not defined" #error "__ADSPBF54x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF54x__ is not defined" #error "__ADSPBF54x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
...@@ -10,8 +10,8 @@ ...@@ -10,8 +10,8 @@
#error "__ADSPBF54x__ is not defined" #error "__ADSPBF54x__ is not defined"
#endif #endif
#if __SILICON_REVISION__ != 0x0000 #if __SILICON_REVISION__ != 0x0001
#error "__SILICON_REVISION__ is not 0x0000" #error "__SILICON_REVISION__ is not 0x0001"
#endif #endif
#ifndef __WORKAROUNDS_ENABLED #ifndef __WORKAROUNDS_ENABLED
......
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