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riscv-gcc-1
Commit a5df2090 by Uros Bizjak Committed by Uros Bizjak
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re PR target/81995 (gcc/reg-stack.c:2073:1: error: unrecognizable insn:) 

	PR target/81995
	* config/i386/i386.md (*<btsc><mode>): Change operand 2
	predicate to register_operand.  Reorder operands.
	(*btr<mode>): Ditto.
	(*<btsc><mode>_mask): Change operand 3 predicate to register_operand.
	(*btr<mode>_mask): Ditto.

testsuite/ChangeLog:

	PR target/81995
	* gcc.target/i386/pr46091-4.c: Add -mregparm=2 for 32bit targets.
	* gcc.target/i386/pr46091-4a.c: Ditto.

From-SVN: r251369
parent 86e03ef9
Showing with 25 additions and 8 deletions
gcc/ChangeLog
2017-08-27 Uros Bizjak <ubizjak@gmail.com>
PR target/81995
* config/i386/i386.md (*<btsc><mode>): Change operand 2
predicate to register_operand. Reorder operands.
(*btr<mode>): Ditto.
(*<btsc><mode>_mask): Change operand 3 predicate to register_operand.
(*btr<mode>_mask): Ditto.
2017-08-25 Steven Munroe <munroesj@gcc.gnu.org>
* config.gcc (powerpc*-*-*): Add xmmintrin.h and mm_malloc.h.
......
gcc/config/i386/i386.md
......@@ -11011,11 +11011,11 @@
[(set (match_operand:SWI48 0 "register_operand" "=r")
(any_or:SWI48
(ashift:SWI48 (const_int 1)
(match_operand:QI 1 "register_operand" "r"))
(match_operand:SWI48 2 "nonimmediate_operand" "0")))
(match_operand:QI 2 "register_operand" "r"))
(match_operand:SWI48 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_BT"
"<btsc>{<imodesuffix>}\t{%<k>1, %0|%0, %<k>1}"
"<btsc>{<imodesuffix>}\t{%<k>2, %0|%0, %<k>2}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
......@@ -11031,7 +11031,7 @@
(and:SI
(match_operand:SI 1 "register_operand")
(match_operand:SI 2 "const_int_operand")) 0))
(match_operand:SWI48 3 "nonimmediate_operand")))
(match_operand:SWI48 3 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"(INTVAL (operands[2]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
== GET_MODE_BITSIZE (<MODE>mode)-1
......@@ -11051,11 +11051,11 @@
[(set (match_operand:SWI48 0 "register_operand" "=r")
(and:SWI48
(rotate:SWI48 (const_int -2)
(match_operand:QI 1 "register_operand" "r"))
(match_operand:SWI48 2 "nonimmediate_operand" "0")))
(match_operand:QI 2 "register_operand" "r"))
(match_operand:SWI48 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_BT"
"btr{<imodesuffix>}\t{%<k>1, %0|%0, %<k>1}"
"btr{<imodesuffix>}\t{%<k>2, %0|%0, %<k>2}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
(set_attr "znver1_decode" "double")
......@@ -11071,7 +11071,7 @@
(and:SI
(match_operand:SI 1 "register_operand")
(match_operand:SI 2 "const_int_operand")) 0))
(match_operand:SWI48 3 "nonimmediate_operand")))
(match_operand:SWI48 3 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"(INTVAL (operands[2]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
== GET_MODE_BITSIZE (<MODE>mode)-1
......
gcc/testsuite/ChangeLog
2017-08-27 Uros Bizjak <ubizjak@gmail.com>
PR target/81995
* gcc.target/i386/pr46091-4.c: Add -mregparm=2 for 32bit targets.
* gcc.target/i386/pr46091-4a.c: Ditto.
2017-08-27 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/81974
......
gcc/testsuite/gcc.target/i386/pr46091-4.c
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-additional-options "-mregparm=2" { target ia32 } } */
int test_1 (int x, int n)
{
......
gcc/testsuite/gcc.target/i386/pr46091-4a.c
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-additional-options "-mregparm=2" { target ia32 } } */
int test_1 (int x, int n)
{
......
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