sparc.md (movdi_insn_sp64_novis): New pattern.

	* config/sparc/sparc.md (movdi_insn_sp64_novis): New pattern.
	(movdi_insn_sp64_vis): Renamed from movdi_insn_sp64.
	(movsf): Don't force any constant to memory if target is integer
	hard register.
	Move fp_zero_operand check below the const0_rtx check.
	(movtf): Likewise. Also allow fp_zero_operand for stores into
	memory.
	(movdf): Likewise. Also allow fp_zero_operand for stores into
	memory and into integer hard registers.
	(clear_df, clear_dfp, movdf_const_intreg_sp32,
	movdf_const_intreg_sp64): Remove.
	(movdf_insn_sp32, movdf_no_e_insn_sp32): Redo constraints and
	conditions.
	(movdf_no_e_insn_v9_sp32): New pattern.
	(movdf_insn_v9only): Remove.
	(movdf_insn_v9only_novis, movdf_insn_v9only_vis): New patterns.
	(movdf_insn_sp64): Remove.
	(movdf_insn_sp64_novis, movdf_insn_sp64_vis): New patterns.
	(movdf_no_e_insn_sp64): Allow storing 0.0 into memory.
	(following splits): Rewrite conditions. Add two new splits
	for storing 0.0 into memory and registers.
	(clear_tf, clear_tf+1, clear_tfp, clear_tfp+1): Remove.
	(movtf_insn_sp32): Redo constraints and conditions.
	(movtf_insn_vis_sp32): New pattern.
	(movtf_no_e_insn_sp32): Redo constraints and conditions.
	(movtf_insn_hq_sp64): Likewise.
	(movtf_insn_hq_vis_sp64): New pattern.
	(movtf_insn_sp64): Redo constraints and conditions.
	(movtf_insn_vis_sp64): New pattern.
	(movtf_no_e_insn_sp64): Redo constraints and conditions.
	(movtf_no_e_insn_sp64+1): New split for storing 0.0L into registers
	or memory.
	* config/sparc/sparc.c (sparc_override_options): Assume v9 if either
	-mvis or -m64 to take down the number of various reload patterns.

From-SVN: r32901

gcc/ChangeLog

@@ -6,6 +6,41 @@
 	non-optimizing TARGET_ARCH32 in DF or DI modes because it is not
 	offsetable.
 
+	* config/sparc/sparc.md (movdi_insn_sp64_novis): New pattern.
+	(movdi_insn_sp64_vis): Renamed from movdi_insn_sp64.
+	(movsf): Don't force any constant to memory if target is integer
+	hard register.
+	Move fp_zero_operand check below the const0_rtx check.
+	(movtf): Likewise. Also allow fp_zero_operand for stores into
+	memory.
+	(movdf): Likewise. Also allow fp_zero_operand for stores into
+	memory and into integer hard registers.
+	(clear_df, clear_dfp, movdf_const_intreg_sp32,
+	movdf_const_intreg_sp64): Remove.
+	(movdf_insn_sp32, movdf_no_e_insn_sp32): Redo constraints and
+	conditions.
+	(movdf_no_e_insn_v9_sp32): New pattern.
+	(movdf_insn_v9only): Remove.
+	(movdf_insn_v9only_novis, movdf_insn_v9only_vis): New patterns.
+	(movdf_insn_sp64): Remove.
+	(movdf_insn_sp64_novis, movdf_insn_sp64_vis): New patterns.
+	(movdf_no_e_insn_sp64): Allow storing 0.0 into memory.
+	(following splits): Rewrite conditions. Add two new splits
+	for storing 0.0 into memory and registers.
+	(clear_tf, clear_tf+1, clear_tfp, clear_tfp+1): Remove.
+	(movtf_insn_sp32): Redo constraints and conditions.
+	(movtf_insn_vis_sp32): New pattern.
+	(movtf_no_e_insn_sp32): Redo constraints and conditions.
+	(movtf_insn_hq_sp64): Likewise.
+	(movtf_insn_hq_vis_sp64): New pattern.
+	(movtf_insn_sp64): Redo constraints and conditions.
+	(movtf_insn_vis_sp64): New pattern.
+	(movtf_no_e_insn_sp64): Redo constraints and conditions.
+	(movtf_no_e_insn_sp64+1): New split for storing 0.0L into registers
+	or memory.
+	* config/sparc/sparc.c (sparc_override_options): Assume v9 if either
+	-mvis or -m64 to take down the number of various reload patterns.
+
 Tue Apr  4 00:41:53 2000  Jeffrey A Law  (law@cygnus.com)
 
 	* pa/pa-64.h: New file.

gcc/config/sparc/sparc.c

@@ -342,6 +342,16 @@ sparc_override_options ()
       target_flags &= ~MASK_FPU_SET;
     }
 
+  /* Don't allow -mvis if FPU is disabled.  */
+  if (! TARGET_FPU)
+    target_flags &= ~MASK_VIS;
+
+  /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
+     are available.
+     -m64 also implies v9.  */
+  if (TARGET_VIS || TARGET_ARCH64)
+    target_flags |= MASK_V9;
+
   /* Use the deprecated v8 insns for sparc64 in 32 bit mode.  */
   if (TARGET_V9 && TARGET_ARCH32)
     target_flags |= MASK_DEPRECATED_V8_INSNS;
@@ -354,10 +364,6 @@ sparc_override_options ()
   if (TARGET_ARCH32)
     target_flags &= ~MASK_STACK_BIAS;
     
-  /* Don't allow -mvis if FPU is disabled.  */
-  if (! TARGET_FPU)
-    target_flags &= ~MASK_VIS;
-
   /* Supply a default value for align_functions.  */
   if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC)
     align_functions = 32;

gcc/config/sparc/sparc.h

@@ -2298,7 +2298,7 @@ LFLGRET"ID":\n\
 #define REG_OK_FOR_BASE_P(X) \
   (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
 
-/* 'T', 'U' are for aligned memory loads which aren't needed for v9.  */
+/* 'T', 'U' are for aligned memory loads which aren't needed for arch64.  */
 
 #define EXTRA_CONSTRAINT(OP, C)				\
    (EXTRA_CONSTRAINT_BASE(OP, C)                        \