2019-05-14 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com\>

gcc/
	* internal-fn.def (SIGNBIT): New.
	* config/aarch64/aarch64-simd.md (signbitv2sf2): New expand
	defined.
	(signbitv4sf2): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/signbitv4sf.c: New test.
	* gcc.target/aarch64/signbitv2sf.c: New test.

From-SVN: r271149

gcc/ChangeLog

+2019-05-14  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com\>
+
+	* internal-fn.def (SIGNBIT): New.
+	* config/aarch64/aarch64-simd.md (signbitv2sf2): New expand
+	defined.
+	(signbitv4sf2): Likewise.
+
 2019-05-14  Chenghua Xu  <paul.hua.gm@gmail.com>
 
 	PR target/90357

gcc/config/aarch64/aarch64-simd.md

@@ -935,6 +935,21 @@
   [(set_attr "type" "neon_ins<q>")]
 )
 
+(define_expand "signbit<mode>2"
+  [(use (match_operand:<V_INT_EQUIV> 0 "register_operand"))
+   (use (match_operand:VDQSF 1 "register_operand"))]
+  "TARGET_SIMD"
+{
+  int shift_amount = GET_MODE_UNIT_BITSIZE (<V_INT_EQUIV>mode) - 1;
+  rtx shift_vector = aarch64_simd_gen_const_vector_dup (<V_INT_EQUIV>mode,
+                                                        shift_amount);
+  operands[1] = lowpart_subreg (<V_INT_EQUIV>mode, operands[1], <MODE>mode);
+
+  emit_insn (gen_aarch64_simd_lshr<v_int_equiv> (operands[0], operands[1],
+                                                 shift_vector));
+  DONE;
+})
+
 (define_insn "aarch64_simd_lshr<mode>"
  [(set (match_operand:VDQ_I 0 "register_operand" "=w")
        (lshiftrt:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")

gcc/internal-fn.def

@@ -217,6 +217,7 @@ DEF_INTERNAL_FLT_FN (LOG10, ECF_CONST, log10, unary)
 DEF_INTERNAL_FLT_FN (LOG1P, ECF_CONST, log1p, unary)
 DEF_INTERNAL_FLT_FN (LOG2, ECF_CONST, log2, unary)
 DEF_INTERNAL_FLT_FN (LOGB, ECF_CONST, logb, unary)
+DEF_INTERNAL_FLT_FN (SIGNBIT, ECF_CONST, signbit, unary)
 DEF_INTERNAL_FLT_FN (SIGNIFICAND, ECF_CONST, significand, unary)
 DEF_INTERNAL_FLT_FN (SIN, ECF_CONST, sin, unary)
 DEF_INTERNAL_FLT_FN (SINH, ECF_CONST, sinh, unary)

gcc/testsuite/ChangeLog

+2019-05-14  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com\>
+
+	* gcc.target/aarch64/signbitv4sf.c: New test.
+	* gcc.target/aarch64/signbitv2sf.c: New test.
+
 2019-05-13  Jonathan Wakely  <jwakely@redhat.com>
 
 	* g++.dg/cpp0x/Wattributes1.C: Adjust dg-error line number to fix

gcc/testsuite/gcc.target/aarch64/signbitv2sf.c

+/* { dg-do run } */
+/* { dg-additional-options "-O3 --save-temps" } */
+
+extern void abort ();
+
+#define N 8
+float in[N] = {1.0, -1.0, -2.0, 3.0, -5.0, -8.0, 13.0, 21.0};
+int out[N];
+
+void
+foo (int *i, float *f)
+{
+  i[0] = __builtin_signbit (f[0]);
+  i[1] = __builtin_signbit (f[1]);
+}
+
+/* { dg-final { scan-assembler-not {-2147483648} } } */
+/* { dg-final { scan-assembler {\tushr\tv[0-9]+.2s, v[0-9]+.2s, 31} } } */
+
+int
+main ()
+{
+  int i;
+
+  foo (out, in);
+  foo (out + 2, in + 2);
+  foo (out + 4, in + 4);
+  foo (out + 6, in + 6);
+
+  for (i = 0; i < N; i++)
+  {
+    if (in[i] >= 0.0 && out[i])
+      abort ();
+    if (in[i] < 0.0 && !out[i])
+      abort ();
+  }
+
+  return 0;
+}
+

gcc/testsuite/gcc.target/aarch64/signbitv4sf.c

+/* { dg-do run } */
+/* { dg-additional-options "-O3 --save-temps" } */
+
+extern void abort ();
+
+#define N 1024
+float in[N] = {1.0, -1.0, -2.0, 3.0, -5.0, -8.0, 13.0, 21.0};
+int out[N];
+
+void
+foo ()
+{
+  int i;
+  for (i = 0; i < N; i++)
+    out[i] = __builtin_signbit (in[i]);
+}
+
+/* { dg-final { scan-assembler-not {-2147483648} } } */
+/* { dg-final { scan-assembler {\tushr\tv[0-9]+.4s, v[0-9]+.4s, 31} } } */
+
+int
+main ()
+{
+  int i;
+
+  foo ();
+
+  for (i = 0; i < N; i++)
+  {
+    if (in[i] >= 0.0 && out[i])
+      abort ();
+    if (in[i] < 0.0 && !out[i])
+      abort ();
+  }
+
+  return 0;
+}
+