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Commit a4931745 by Chung-Ju Wu Committed by Chung-Ju Wu
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[NDS32] Implement more C ISR extension. 

gcc/
	* config.gcc (nds32*): Add nds32_isr.h and nds32_init.inc in
	extra_headers.
	* common/config/nds32/nds32-common.c (nds32_handle_option): Handle
	OPT_misr_secure_ case.
	* config/nds32/nds32-isr.c: Implementation of backward compatibility.
	* config/nds32/nds32-protos.h (nds32_isr_function_critical_p): New.
	* config/nds32/nds32.c (nds32_attribute_table): Add critical and
	secure attribute.
	* config/nds32/nds32.h (nds32_isr_nested_type): Add NDS32_CRITICAL.
	(nds32_isr_info): New field security_level.
	(TARGET_ISR_VECTOR_SIZE_4_BYTE): New macro.
	* config/nds32/nds32.md (return_internal): Consider critical attribute.
	* config/nds32/nds32.opt (misr-secure): New option.
	* config/nds32/nds32_init.inc: New file.
	* config/nds32/nds32_isr.h: New file.

libgcc/
	* config/nds32/t-nds32-isr: Rearrange object dependency.
	* config/nds32/initfini.c: Add dwarf2 unwinding support.
	* config/nds32/isr-library/adj_intr_lvl.inc: Consider new extensions
	and registers usage.
	* config/nds32/isr-library/excp_isr.S: Ditto.
	* config/nds32/isr-library/intr_isr.S: Ditto.
	* config/nds32/isr-library/reset.S: Ditto.
	* config/nds32/isr-library/restore_all.inc: Ditto.
	* config/nds32/isr-library/restore_mac_regs.inc: Ditto.
	* config/nds32/isr-library/restore_partial.inc: Ditto.
	* config/nds32/isr-library/restore_usr_regs.inc: Ditto.
	* config/nds32/isr-library/save_all.inc: Ditto.
	* config/nds32/isr-library/save_mac_regs.inc: Ditto.
	* config/nds32/isr-library/save_partial.inc: Ditto.
	* config/nds32/isr-library/save_usr_regs.inc: Ditto.
	* config/nds32/isr-library/vec_vid*.S: Consider 4-byte vector size.

From-SVN: r263493
parent 39d2c7ed
Showing with 1053 additions and 251 deletions
gcc/ChangeLog
2018-08-12 Chung-Ju Wu <jasonwucj@gmail.com>
* config.gcc (nds32*): Add nds32_isr.h and nds32_init.inc in
extra_headers.
* common/config/nds32/nds32-common.c (nds32_handle_option): Handle
OPT_misr_secure_ case.
* config/nds32/nds32-isr.c: Implementation of backward compatibility.
* config/nds32/nds32-protos.h (nds32_isr_function_critical_p): New.
* config/nds32/nds32.c (nds32_attribute_table): Add critical and
secure attribute.
* config/nds32/nds32.h (nds32_isr_nested_type): Add NDS32_CRITICAL.
(nds32_isr_info): New field security_level.
(TARGET_ISR_VECTOR_SIZE_4_BYTE): New macro.
* config/nds32/nds32.md (return_internal): Consider critical attribute.
* config/nds32/nds32.opt (misr-secure): New option.
* config/nds32/nds32_init.inc: New file.
* config/nds32/nds32_isr.h: New file.
2018-08-11 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum.
......
gcc/common/config/nds32/nds32-common.c
......@@ -53,6 +53,16 @@ nds32_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
return true;
case OPT_misr_secure_:
/* Check the valid security level: 0 1 2 3. */
if (value < 0 || value > 3)
{
error_at (loc, "for the option -misr-secure=X, the valid X "
"must be: 0, 1, 2, or 3");
return false;
}
return true;
case OPT_mcache_block_size_:
/* Check valid value: 4 8 16 32 64 128 256 512. */
if (exact_log2 (value) < 2 || exact_log2 (value) > 9)
......
gcc/config.gcc
......@@ -447,7 +447,7 @@ mips*-*-*)
;;
nds32*)
cpu_type=nds32
extra_headers="nds32_intrinsic.h"
extra_headers="nds32_intrinsic.h nds32_isr.h nds32_init.inc"
case ${target} in
nds32*-*-linux*)
extra_options="${extra_options} nds32/nds32-linux.opt"
......
gcc/config/nds32/nds32-protos.h
......@@ -307,6 +307,7 @@ extern void nds32_construct_isr_vectors_information (tree, const char *);
extern void nds32_asm_file_start_for_isr (void);
extern void nds32_asm_file_end_for_isr (void);
extern bool nds32_isr_function_p (tree);
extern bool nds32_isr_function_critical_p (tree);
/* Auxiliary functions for cost calculation. */
......
gcc/config/nds32/nds32.c
......@@ -305,6 +305,7 @@ static const struct attribute_spec nds32_attribute_table[] =
{ "nested", 0, 0, false, false, false, false, NULL, NULL },
{ "not_nested", 0, 0, false, false, false, false, NULL, NULL },
{ "nested_ready", 0, 0, false, false, false, false, NULL, NULL },
{ "critical", 0, 0, false, false, false, false, NULL, NULL },
/* The attributes describing isr register save scheme. */
{ "save_all", 0, 0, false, false, false, false, NULL, NULL },
......@@ -314,6 +315,9 @@ static const struct attribute_spec nds32_attribute_table[] =
{ "nmi", 1, 1, false, false, false, false, NULL, NULL },
{ "warm", 1, 1, false, false, false, false, NULL, NULL },
/* The attributes describing isr security level. */
{ "secure", 1, 1, false, false, false, false, NULL, NULL },
/* The attribute telling no prologue/epilogue. */
{ "naked", 0, 0, false, false, false, false, NULL, NULL },
......@@ -518,7 +522,7 @@ nds32_compute_stack_frame (void)
}
/* Check if this function can omit prologue/epilogue code fragment.
If there is 'no_prologue'/'naked' attribute in this function,
If there is 'no_prologue'/'naked'/'secure' attribute in this function,
we can set 'naked_p' flag to indicate that
we do not have to generate prologue/epilogue.
Or, if all the following conditions succeed,
......@@ -533,6 +537,7 @@ nds32_compute_stack_frame (void)
we do not need to adjust $sp. */
if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl))
|| lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
|| lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl))
|| (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM
&& cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM
&& cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM
......@@ -2307,14 +2312,17 @@ nds32_function_ok_for_sibcall (tree decl,
/* 1. Do not apply sibling call if -mv3push is enabled,
because pop25 instruction also represents return behavior.
2. If this function is a variadic function, do not apply sibling call
2. If this function is a isr function, do not apply sibling call
because it may perform the behavior that user does not expect.
3. If this function is a variadic function, do not apply sibling call
because the stack layout may be a mess.
3. We don't want to apply sibling call optimization for indirect
4. We don't want to apply sibling call optimization for indirect
sibcall because the pop behavior in epilogue may pollute the
content of caller-saved regsiter when the register is used for
indirect sibcall.
4. In pic mode, it may use some registers for PLT call. */
5. In pic mode, it may use some registers for PLT call. */
return (!TARGET_V3PUSH
&& !nds32_isr_function_p (current_function_decl)
&& (cfun->machine->va_args_size == 0)
&& decl
&& !flag_pic);
......@@ -3968,6 +3976,38 @@ nds32_insert_attributes (tree decl, tree *attributes)
excp = lookup_attribute ("exception", func_attrs);
reset = lookup_attribute ("reset", func_attrs);
/* The following code may use attribute arguments. If there is no
argument from source code, it will cause segmentation fault.
Therefore, return dircetly and report error message later. */
if ((intr && TREE_VALUE (intr) == NULL)
|| (excp && TREE_VALUE (excp) == NULL)
|| (reset && TREE_VALUE (reset) == NULL))
return;
/* ------------------------------------------------------------- */
/* FIXME:
FOR BACKWARD COMPATIBILITY, we need to support following patterns:
__attribute__((interrupt("XXX;YYY;id=ZZZ")))
__attribute__((exception("XXX;YYY;id=ZZZ")))
__attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ")))
If interrupt/exception/reset appears and its argument is a
STRING_CST, we will use other functions to parse string in the
nds32_construct_isr_vectors_information() and then set necessary
isr information in the nds32_isr_vectors[] array. Here we can
just return immediately to avoid new-syntax checking. */
if (intr != NULL_TREE
&& TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST)
return;
if (excp != NULL_TREE
&& TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST)
return;
if (reset != NULL_TREE
&& TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST)
return;
/* ------------------------------------------------------------- */
if (intr || excp)
{
/* Deal with interrupt/exception. */
......@@ -4211,6 +4251,16 @@ nds32_cpu_cpp_builtins(struct cpp_reader *pfile)
builtin_define ("__nds32__");
builtin_define ("__NDS32__");
/* We need to provide builtin macro to describe the size of
each vector for interrupt handler under elf toolchain. */
if (!TARGET_LINUX_ABI)
{
if (TARGET_ISR_VECTOR_SIZE_4_BYTE)
builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__");
else
builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__");
}
if (TARGET_HARD_FLOAT)
builtin_define ("__NDS32_ABI_2FP_PLUS__");
else
......
gcc/config/nds32/nds32.h
......@@ -367,7 +367,8 @@ enum nds32_isr_nested_type
{
NDS32_NESTED,
NDS32_NOT_NESTED,
NDS32_NESTED_READY
NDS32_NESTED_READY,
NDS32_CRITICAL
};
/* Define structure to record isr information.
......@@ -395,6 +396,13 @@ struct nds32_isr_info
unless user specifies attribute to change it. */
enum nds32_isr_nested_type nested_type;
/* Secure isr level.
Currently we have 0-3 security level.
It should be set to 0 by default.
For security processors, this is determined by secure
attribute or compiler options. */
unsigned int security_level;
/* Total vectors.
The total vectors = interrupt + exception numbers + reset.
It should be set to 0 by default.
......@@ -849,8 +857,10 @@ enum nds32_builtins
/* ------------------------------------------------------------------------ */
#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
#define TARGET_ISR_VECTOR_SIZE_4_BYTE \
(nds32_isr_vector_size == 4)
#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
#define TARGET_ISA_V3 \
(nds32_arch_option == ARCH_V3 \
|| nds32_arch_option == ARCH_V3J \
......
gcc/config/nds32/nds32.md
......@@ -1993,6 +1993,9 @@
[(simple_return)]
""
{
if (nds32_isr_function_critical_p (current_function_decl))
return "iret";
if (TARGET_16_BIT)
return "ret5";
else
......@@ -2001,9 +2004,11 @@
[(set_attr "type" "branch")
(set_attr "enabled" "yes")
(set (attr "length")
(if_then_else (match_test "TARGET_16_BIT")
(const_int 2)
(const_int 4)))])
(if_then_else (match_test "nds32_isr_function_critical_p (current_function_decl)")
(const_int 4)
(if_then_else (match_test "TARGET_16_BIT")
(const_int 2)
(const_int 4))))])
;; ----------------------------------------------------------------------------
......
gcc/config/nds32/nds32.opt
......@@ -158,6 +158,10 @@ misr-vector-size=
Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
Specify the size of each interrupt vector, which must be 4 or 16.
misr-secure=
Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0)
Specify the security level of c-isr for the whole file.
mcache-block-size=
Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
Specify the size of each cache block, which must be a power of 2 between 4 and 512.
......
gcc/config/nds32/nds32_init.inc 0 → 100644
/*
* nds32_init.inc
*
* NDS32 architecture startup assembler header file
*
*/
.macro nds32_init
! Initialize GP for data access
la $gp, _SDA_BASE_
#if defined(__NDS32_EXT_EX9__)
! Check HW for EX9
mfsr $r0, $MSC_CFG
li $r1, (1 << 24)
and $r2, $r0, $r1
beqz $r2, 1f
! Initialize the table base of EX9 instruction
la $r0, _ITB_BASE_
mtusr $r0, $ITB
1:
#endif
#if defined(__NDS32_EXT_FPU_DP__) || defined(__NDS32_EXT_FPU_SP__)
! Enable FPU
mfsr $r0, $FUCOP_CTL
ori $r0, $r0, #0x1
mtsr $r0, $FUCOP_CTL
dsb
! Enable denormalized flush-to-Zero mode
fmfcsr $r0
ori $r0,$r0,#0x1000
fmtcsr $r0
dsb
#endif
! Initialize default stack pointer
la $sp, _stack
.endm
libgcc/ChangeLog
2018-08-12 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/t-nds32-isr: Rearrange object dependency.
* config/nds32/initfini.c: Add dwarf2 unwinding support.
* config/nds32/isr-library/adj_intr_lvl.inc: Consider new extensions
and registers usage.
* config/nds32/isr-library/excp_isr.S: Ditto.
* config/nds32/isr-library/intr_isr.S: Ditto.
* config/nds32/isr-library/reset.S: Ditto.
* config/nds32/isr-library/restore_all.inc: Ditto.
* config/nds32/isr-library/restore_mac_regs.inc: Ditto.
* config/nds32/isr-library/restore_partial.inc: Ditto.
* config/nds32/isr-library/restore_usr_regs.inc: Ditto.
* config/nds32/isr-library/save_all.inc: Ditto.
* config/nds32/isr-library/save_mac_regs.inc: Ditto.
* config/nds32/isr-library/save_partial.inc: Ditto.
* config/nds32/isr-library/save_usr_regs.inc: Ditto.
* config/nds32/isr-library/vec_vid*.S: Consider 4-byte vector size.
2018-08-11 John David Anglin <danglin@gcc.gnu.org>
* config/pa/linux-atomic.c: Update comment.
......
libgcc/config/nds32/initfini.c
......@@ -25,6 +25,10 @@
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include <stddef.h>
/* Need header file for `struct object' type. */
#include "../libgcc/unwind-dw2-fde.h"
/* Declare a pointer to void function type. */
typedef void (*func_ptr) (void);
......@@ -42,11 +46,59 @@ typedef void (*func_ptr) (void);
refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
symbol in crtinit.o, where they are defined. */
static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors")))
= { (func_ptr) (-1) };
static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"), used))
= { (func_ptr) 0 };
static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"), used))
= { (func_ptr) 0 };
#ifdef SUPPORT_UNWINDING_DWARF2
/* Preparation of exception handling with dwar2 mechanism registration. */
static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
= { (func_ptr) (-1) };
asm ("\n\
.section .eh_frame,\"aw\",@progbits\n\
.global __EH_FRAME_BEGIN__\n\
.type __EH_FRAME_BEGIN__, @object\n\
.align 2\n\
__EH_FRAME_BEGIN__:\n\
! Beginning location of eh_frame section\n\
.previous\n\
");
extern func_ptr __EH_FRAME_BEGIN__[];
/* Note that the following two functions are going to be chained into
constructor and destructor list, repectively. So these two declarations
must be placed after __CTOR_LIST__ and __DTOR_LIST. */
extern void __nds32_register_eh(void) __attribute__((constructor, used));
extern void __nds32_deregister_eh(void) __attribute__((destructor, used));
/* Register the exception handling table as the first constructor. */
void
__nds32_register_eh (void)
{
static struct object object;
if (__register_frame_info)
__register_frame_info (__EH_FRAME_BEGIN__, &object);
}
/* Unregister the exception handling table as a deconstructor. */
void
__nds32_deregister_eh (void)
{
static int completed = 0;
if (completed)
return;
if (__deregister_frame_info)
__deregister_frame_info (__EH_FRAME_BEGIN__);
completed = 1;
}
#endif
/* Run all the global destructors on exit from the program. */
......@@ -63,7 +115,7 @@ static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
same particular root executable or shared library file. */
static void __do_global_dtors (void)
asm ("__do_global_dtors") __attribute__ ((section (".text")));
asm ("__do_global_dtors") __attribute__ ((section (".text"), used));
static void
__do_global_dtors (void)
......@@ -116,23 +168,37 @@ void *__dso_handle = 0;
last, these words naturally end up at the very ends of the two lists
contained in these two sections. */
static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors")))
static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"), used))
= { (func_ptr) 0 };
static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors")))
static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"), used))
= { (func_ptr) 0 };
#ifdef SUPPORT_UNWINDING_DWARF2
/* ZERO terminator in .eh_frame section. */
asm ("\n\
.section .eh_frame,\"aw\",@progbits\n\
.global __EH_FRAME_END__\n\
.type __EH_FRAME_END__, @object\n\
.align 2\n\
__EH_FRAME_END__:\n\
! End location of eh_frame section with ZERO terminator\n\
.word 0\n\
.previous\n\
");
#endif
/* Run all global constructors for the program.
Note that they are run in reverse order. */
static void __do_global_ctors (void)
asm ("__do_global_ctors") __attribute__ ((section (".text")));
asm ("__do_global_ctors") __attribute__ ((section (".text"), used));
static void
__do_global_ctors (void)
{
func_ptr *p;
for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
for (p = __CTOR_END__ - 1; *p; p--)
(*p) ();
}
......
libgcc/config/nds32/isr-library/adj_intr_lvl.inc
......@@ -26,13 +26,26 @@
.macro ADJ_INTR_LVL
#if defined(NDS32_NESTED) /* Nested handler. */
mfsr $r3, $PSW
/* By substracting 1 from $PSW, we can lower PSW.INTL
and enable GIE simultaneously. */
addi $r3, $r3, #-0x1
#if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
#endif
mtsr $r3, $PSW
#elif defined(NDS32_NESTED_READY) /* Nested ready handler. */
/* Save ipc and ipsw and lower INT level. */
mfsr $r3, $PSW
addi $r3, $r3, #-0x2
#if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
#endif
mtsr $r3, $PSW
#else /* Not nested handler. */
#if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
mfsr $r3, $PSW
ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */
mtsr $r3, $PSW
#endif
#endif
.endm
libgcc/config/nds32/isr-library/excp_isr.S
......@@ -23,6 +23,7 @@
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_usr_regs.inc"
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
......@@ -32,35 +33,33 @@
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_mac_regs.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_mac_regs.inc"
#include "restore_usr_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/*
First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR: Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT: Nested Type
ns: nested
nn: not nested
nr: nested ready
*/
/*
This is original 16-byte vector size version.
*/
/* First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR -- Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT -- Nested Type
ns: nested
nn: not nested
nr: nested ready */
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_e_sa_ns
......@@ -91,21 +90,26 @@ _nds32_e_ps_nn:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/*
This is 16-byte vector size version.
The vector id was restored into $r0 in vector by compiler.
*/
/* For 4-byte vector size version, the vector id is
extracted from $ITYPE and is set into $r0 by library.
For 16-byte vector size version, the vector id
is set into $r0 in vector section by compiler. */
/* Save used registers. */
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL
#else
SAVE_PARTIAL
#endif
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_00
lw $r2, [$r2 + $r0 << #2]
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
/* Restore used registers. */
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
......@@ -113,6 +117,7 @@ _nds32_e_ps_nn:
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_e_sa_ns, .-_nds32_e_sa_ns
......
libgcc/config/nds32/isr-library/intr_isr.S
......@@ -23,6 +23,7 @@
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_usr_regs.inc"
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
......@@ -32,35 +33,33 @@
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_mac_regs.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_mac_regs.inc"
#include "restore_usr_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/*
First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR: Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT: Nested Type
ns: nested
nn: not nested
nr: nested ready
*/
/*
This is original 16-byte vector size version.
*/
/* First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR -- Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT -- Nested Type
ns: nested
nn: not nested
nr: nested ready */
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_i_sa_ns
......@@ -91,21 +90,36 @@ _nds32_i_ps_nn:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/*
This is 16-byte vector size version.
The vector id was restored into $r0 in vector by compiler.
*/
/* For 4-byte vector size version, the vector id is
extracted from $ITYPE and is set into $r0 by library.
For 16-byte vector size version, the vector id
is set into $r0 in vector section by compiler. */
/* Save used registers first. */
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL
#else
SAVE_PARTIAL
#endif
/* Prepare to call 2nd level handler. */
/* According to vector size, we need to have different implementation. */
#if __NDS32_ISR_VECTOR_SIZE_4__
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_00
lw $r2, [$r2 + $r0 << #2]
addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */
lw $r2, [$r2 + $r0 << #2]
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
/* Restore used registers. */
#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
......@@ -113,6 +127,7 @@ _nds32_i_ps_nn:
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_i_sa_ns, .-_nds32_i_sa_ns
......
libgcc/config/nds32/isr-library/reset.S
......@@ -26,22 +26,18 @@
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
.weak _SDA_BASE_ /* For reset handler only. */
.weak _FP_BASE_ /* For reset handler only. */
.weak _nds32_init_mem /* User defined memory initialization function. */
.globl _start
.globl _nds32_reset
.type _nds32_reset, @function
_nds32_reset:
_start:
#ifdef NDS32_EXT_EX9
.no_ex9_begin
#endif
/* Handle NMI and warm boot if any of them exists. */
beqz $sp, 1f /* Reset, NMI or warm boot? */
/* Either NMI or warm boot; save all regs. */
/* Preserve registers for context-switching. */
#ifdef __NDS32_REDUCED_REGS__
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
/* For 16-reg mode. */
smw.adm $r0, [$sp], $r10, #0x0
smw.adm $r15, [$sp], $r15, #0xf
......@@ -49,10 +45,9 @@ _start:
/* For 32-reg mode. */
smw.adm $r0, [$sp], $r27, #0xf
#endif
#ifdef NDS32_EXT_IFC
#if __NDS32_EXT_IFC__
mfusr $r1, $IFC_LP
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
stack 8-byte alignment. */
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte alignment. */
#endif
la $gp, _SDA_BASE_ /* Init GP for small data access. */
......@@ -71,12 +66,11 @@ _start:
bnez $r0, 1f /* If fail to resume, do cold boot. */
/* Restore registers for context-switching. */
#ifdef NDS32_EXT_IFC
lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
stack 8-byte alignment. */
#if __NDS32_EXT_IFC__
lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep stack 8-byte alignment. */
mtusr $r1, $IFC_LP
#endif
#ifdef __NDS32_REDUCED_REGS__
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
/* For 16-reg mode. */
lmw.bim $r15, [$sp], $r15, #0xf
lmw.bim $r0, [$sp], $r10, #0x0
......@@ -88,6 +82,17 @@ _start:
1: /* Cold boot. */
#if __NDS32_ISR_VECTOR_SIZE_4__
/* With vector ID feature for v3 architecture, default vector size is 4-byte. */
/* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */
mfsr $r0, $IVB
li $r1, #0xc000
or $r0, $r0, $r1
xor $r0, $r0, $r1
mtsr $r0, $IVB
dsb
#else
/* There is no vector ID feature, so the vector size must be 16-byte. */
/* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */
mfsr $r0, $IVB
li $r1, #0xffff3fff
......@@ -95,36 +100,54 @@ _start:
ori $r0, $r0, #0x4000
mtsr $r0, $IVB
dsb
#endif
la $gp, _SDA_BASE_ /* Init $gp. */
la $fp, _FP_BASE_ /* Init $fp. */
la $sp, _stack /* Init $sp. */
#ifdef NDS32_EXT_EX9
/*
* Initialize the table base of EX9 instruction
* ex9 generation needs to disable before the ITB is set
*/
mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */
#if __NDS32_EXT_EX9__
.L_init_itb:
/* Initialization for Instruction Table Base (ITB).
The symbol _ITB_BASE_ is determined by Linker.
Set $ITB only if MSC_CFG.EIT (cr4.b'24) is set. */
mfsr $r0, $MSC_CFG
srli $r0, $r0, 24
andi $r0, $r0, 0x1
beqz $r0, 4f /* Zero means HW does not support EX9. */
la $r0, _ITB_BASE_ /* Init $ITB. */
beqz $r0, 4f /* Fall through ? */
la $r0, _ITB_BASE_
mtusr $r0, $ITB
.no_ex9_end
4:
#endif
la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem
may written by C language. */
#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__
.L_init_fpu:
/* Initialize FPU
Set FUCOP_CTL.CP0EN (fucpr.b'0). */
mfsr $r0, $FUCOP_CTL
ori $r0, $r0, 0x1
mtsr $r0, $FUCOP_CTL
dsb
/* According to [bugzilla #9425], set flush-to-zero mode.
That is, set $FPCSR.DNZ(b'12) = 1. */
FMFCSR $r0
ori $r0, $r0, 0x1000
FMTCSR $r0
dsb
#endif
/* Call DRAM init. _nds32_init_mem may written by C language. */
la $r15, _nds32_init_mem
beqz $r15, 6f
jral $r15
6:
l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */
jral $r15
/* Reset handler() should never return in a RTOS or non-OS system.
In case it does return, an exception will be generated.
This exception will be caught either by default break handler or by EDM.
Default break handle may just do an infinite loop.
EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
/* Reset handler() should never return in a RTOS or non-OS system.
In case it does return, an exception will be generated.
This exception will be caught either by default break handler or by EDM.
Default break handle may just do an infinite loop.
EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
5:
break #0x7fff
.size _nds32_reset, .-_nds32_reset
libgcc/config/nds32/isr-library/restore_all.inc
......@@ -31,15 +31,11 @@
mtsr $r2, $IPSW
RESTORE_FPU_REGS
RESTORE_MAC_REGS
#ifdef NDS32_EXT_IFC
lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
stack 8-byte alignment. */
mtusr $r1, $IFC_LP
#endif
#ifdef __NDS32_REDUCED_REGS__
RESTORE_USR_REGS
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
lmw.bim $r0, [$sp], $r10, #0x0 /* Restore all regs. */
lmw.bim $r15, [$sp], $r15, #0xf
#else /* not __NDS32_REDUCED_REGS__ */
#else
lmw.bim $r0, [$sp], $r27, #0xf /* Restore all regs. */
#endif
.endm
libgcc/config/nds32/isr-library/restore_mac_regs.inc
......@@ -24,7 +24,7 @@
<http://www.gnu.org/licenses/>. */
.macro RESTORE_MAC_REGS
#ifdef NDS32_DX_REGS
#if __NDS32_DX_REGS__
lmw.bim $r1, [$sp], $r4, #0x0
mtusr $r1, $d0.lo
mtusr $r2, $d0.hi
......
libgcc/config/nds32/isr-library/restore_partial.inc
......@@ -31,15 +31,11 @@
mtsr $r1, $IPC /* Set IPC. */
mtsr $r2, $IPSW /* Set IPSW. */
#endif
RESTORE_FPU_REGS
RESTORE_MAC_REGS
#ifdef NDS32_EXT_IFC
lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
stack 8-byte alignment. */
mtusr $r1, $IFC_LP
#endif
RESTORE_FPU_REGS
RESTORE_MAC_REGS
RESTORE_USR_REGS
lmw.bim $r0, [$sp], $r5, #0x0 /* Restore all regs. */
#ifdef __NDS32_REDUCED_REGS__
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
lmw.bim $r15, [$sp], $r15, #0x2
#else
lmw.bim $r15, [$sp], $r27, #0x2 /* Restore all regs. */
......
libgcc/config/nds32/isr-library/restore_usr_regs.inc 0 → 100644
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2018 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.macro RESTORE_USR_REGS
#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
lmw.bim $r1, [$sp], $r4, #0x0
mtusr $r1, $IFC_LP
mtusr $r2, $LB
mtusr $r3, $LE
mtusr $r4, $LC
#elif __NDS32_EXT_IFC__
lmw.bim $r1, [$sp], $r2, #0x0
mtusr $r1, $IFC_LP
#elif __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__
lmw.bim $r1, [$sp], $r4, #0x0
mtusr $r1, $LB
mtusr $r2, $LE
mtusr $r3, $LC
#endif
.endm
libgcc/config/nds32/isr-library/save_all.inc
......@@ -23,45 +23,42 @@
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.macro SAVE_ALL_4B
#ifdef __NDS32_REDUCED_REGS__
#if __NDS32_ISR_VECTOR_SIZE_4__
/* If vector size is 4-byte, we have to save registers
in the macro implementation. */
.macro SAVE_ALL
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
smw.adm $r15, [$sp], $r15, #0xf
smw.adm $r0, [$sp], $r10, #0x0
#else /* not __NDS32_REDUCED_REGS__ */
#else
smw.adm $r0, [$sp], $r27, #0xf
#endif /* not __NDS32_REDUCED_REGS__ */
#ifdef NDS32_EXT_IFC
mfusr $r1, $IFC_LP
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
stack 8-byte alignment. */
#endif
SAVE_MAC_REGS
SAVE_FPU_REGS
SAVE_USR_REGS
SAVE_MAC_REGS
SAVE_FPU_REGS
mfsr $r1, $IPC /* Get IPC. */
mfsr $r2, $IPSW /* Get IPSW. */
smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
mfsr $r0, $ITYPE /* Get VID to $r0. */
srli $r0, $r0, #5
#ifdef __NDS32_ISA_V2__
andi $r0, $r0, #127
#else
fexti33 $r0, #6
#endif
.endm
#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
/* If vector size is 16-byte, some works can be done in
the vector section generated by compiler, so that we
can implement less in the macro. */
.macro SAVE_ALL
/* SAVE_REG_TBL code has been moved to
vector table generated by compiler. */
#ifdef NDS32_EXT_IFC
mfusr $r1, $IFC_LP
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
stack 8-byte alignment. */
#endif
SAVE_MAC_REGS
SAVE_FPU_REGS
SAVE_USR_REGS
SAVE_MAC_REGS
SAVE_FPU_REGS
mfsr $r1, $IPC /* Get IPC. */
mfsr $r2, $IPSW /* Get IPSW. */
smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
.endm
#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
libgcc/config/nds32/isr-library/save_mac_regs.inc
......@@ -24,7 +24,7 @@
<http://www.gnu.org/licenses/>. */
.macro SAVE_MAC_REGS
#ifdef NDS32_DX_REGS
#if __NDS32_DX_REGS__
mfusr $r1, $d0.lo
mfusr $r2, $d0.hi
mfusr $r3, $d1.lo
......
libgcc/config/nds32/isr-library/save_partial.inc
......@@ -23,20 +23,20 @@
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.macro SAVE_PARTIAL_4B
#ifdef __NDS32_REDUCED_REGS__
#if __NDS32_ISR_VECTOR_SIZE_4__
/* If vector size is 4-byte, we have to save registers
in the macro implementation. */
.macro SAVE_PARTIAL
#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
smw.adm $r15, [$sp], $r15, #0x2
#else /* not __NDS32_REDUCED_REGS__ */
#else
smw.adm $r15, [$sp], $r27, #0x2
#endif /* not __NDS32_REDUCED_REGS__ */
smw.adm $r0, [$sp], $r5, #0x0
#ifdef NDS32_EXT_IFC
mfusr $r1, $IFC_LP
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
stack 8-byte alignment. */
#endif
SAVE_MAC_REGS
SAVE_FPU_REGS
smw.adm $r0, [$sp], $r5, #0x0
SAVE_USR_REGS
SAVE_MAC_REGS
SAVE_FPU_REGS
#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
mfsr $r1, $IPC /* Get IPC. */
mfsr $r2, $IPSW /* Get IPSW. */
......@@ -44,26 +44,24 @@
#endif
mfsr $r0, $ITYPE /* Get VID to $r0. */
srli $r0, $r0, #5
#ifdef __NDS32_ISA_V2__
andi $r0, $r0, #127
#else
fexti33 $r0, #6
#endif
.endm
#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
/* If vector size is 16-byte, some works can be done in
the vector section generated by compiler, so that we
can implement less in the macro. */
.macro SAVE_PARTIAL
/* SAVE_CALLER_REGS code has been moved to
vector table generated by compiler. */
#ifdef NDS32_EXT_IFC
mfusr $r1, $IFC_LP
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
stack 8-byte alignment. */
#endif
SAVE_MAC_REGS
SAVE_FPU_REGS
SAVE_USR_REGS
SAVE_MAC_REGS
SAVE_FPU_REGS
#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
mfsr $r1, $IPC /* Get IPC. */
mfsr $r2, $IPSW /* Get IPSW. */
smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
#endif
.endm
#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
libgcc/config/nds32/isr-library/save_usr_regs.inc 0 → 100644
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2018 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.macro SAVE_USR_REGS
/* Store User Special Registers according to supported ISA extension
!!! WATCH OUT !!! Take care of 8-byte alignment issue. */
#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
mfusr $r1, $IFC_LP
mfusr $r2, $LB
mfusr $r3, $LE
mfusr $r4, $LC
smw.adm $r1, [$sp], $r4, #0x0 /* Save even. Ok! */
#elif __NDS32_EXT_IFC__
mfusr $r1, $IFC_LP
smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte aligned. */
#elif (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__)
mfusr $r1, $LB
mfusr $r2, $LE
mfusr $r3, $LC
smw.adm $r1, [$sp], $r4, #0x0 /* Save extra $r4 to keep stack 8-byte aligned. */
#endif
.endm
libgcc/config/nds32/isr-library/vec_vid00.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.00, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_00
.type _nds32_vector_00, @function
_nds32_vector_00:
......
libgcc/config/nds32/isr-library/vec_vid01.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.01, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_01
.type _nds32_vector_01, @function
_nds32_vector_01:
......
libgcc/config/nds32/isr-library/vec_vid02.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.02, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_02
.type _nds32_vector_02, @function
_nds32_vector_02:
......
libgcc/config/nds32/isr-library/vec_vid03.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.03, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_03
.type _nds32_vector_03, @function
_nds32_vector_03:
......
libgcc/config/nds32/isr-library/vec_vid04.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.04, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_04
.type _nds32_vector_04, @function
_nds32_vector_04:
......
libgcc/config/nds32/isr-library/vec_vid05.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.05, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_05
.type _nds32_vector_05, @function
_nds32_vector_05:
......
libgcc/config/nds32/isr-library/vec_vid06.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.06, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_06
.type _nds32_vector_06, @function
_nds32_vector_06:
......
libgcc/config/nds32/isr-library/vec_vid07.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.07, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_07
.type _nds32_vector_07, @function
_nds32_vector_07:
......
libgcc/config/nds32/isr-library/vec_vid08.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.08, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_08
.type _nds32_vector_08, @function
_nds32_vector_08:
......
libgcc/config/nds32/isr-library/vec_vid09.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.09, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_09
.type _nds32_vector_09, @function
_nds32_vector_09:
......
libgcc/config/nds32/isr-library/vec_vid10.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.10, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_10
.type _nds32_vector_10, @function
_nds32_vector_10:
......
libgcc/config/nds32/isr-library/vec_vid11.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.11, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_11
.type _nds32_vector_11, @function
_nds32_vector_11:
......
libgcc/config/nds32/isr-library/vec_vid12.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.12, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_12
.type _nds32_vector_12, @function
_nds32_vector_12:
......
libgcc/config/nds32/isr-library/vec_vid13.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.13, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_13
.type _nds32_vector_13, @function
_nds32_vector_13:
......
libgcc/config/nds32/isr-library/vec_vid14.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.14, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_14
.type _nds32_vector_14, @function
_nds32_vector_14:
......
libgcc/config/nds32/isr-library/vec_vid15.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.15, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_15
.type _nds32_vector_15, @function
_nds32_vector_15:
......
libgcc/config/nds32/isr-library/vec_vid16.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.16, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_16
.type _nds32_vector_16, @function
_nds32_vector_16:
......
libgcc/config/nds32/isr-library/vec_vid17.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.17, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_17
.type _nds32_vector_17, @function
_nds32_vector_17:
......
libgcc/config/nds32/isr-library/vec_vid18.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.18, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_18
.type _nds32_vector_18, @function
_nds32_vector_18:
......
libgcc/config/nds32/isr-library/vec_vid19.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.19, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_19
.type _nds32_vector_19, @function
_nds32_vector_19:
......
libgcc/config/nds32/isr-library/vec_vid20.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.20, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_20
.type _nds32_vector_20, @function
_nds32_vector_20:
......
libgcc/config/nds32/isr-library/vec_vid21.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.21, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_21
.type _nds32_vector_21, @function
_nds32_vector_21:
......
libgcc/config/nds32/isr-library/vec_vid22.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.22, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_22
.type _nds32_vector_22, @function
_nds32_vector_22:
......
libgcc/config/nds32/isr-library/vec_vid23.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.23, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_23
.type _nds32_vector_23, @function
_nds32_vector_23:
......
libgcc/config/nds32/isr-library/vec_vid24.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.24, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_24
.type _nds32_vector_24, @function
_nds32_vector_24:
......
libgcc/config/nds32/isr-library/vec_vid25.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.25, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_25
.type _nds32_vector_25, @function
_nds32_vector_25:
......
libgcc/config/nds32/isr-library/vec_vid26.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.26, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_26
.type _nds32_vector_26, @function
_nds32_vector_26:
......
libgcc/config/nds32/isr-library/vec_vid27.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.27, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_27
.type _nds32_vector_27, @function
_nds32_vector_27:
......
libgcc/config/nds32/isr-library/vec_vid28.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.28, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_28
.type _nds32_vector_28, @function
_nds32_vector_28:
......
libgcc/config/nds32/isr-library/vec_vid29.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.29, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_29
.type _nds32_vector_29, @function
_nds32_vector_29:
......
libgcc/config/nds32/isr-library/vec_vid30.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.30, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_30
.type _nds32_vector_30, @function
_nds32_vector_30:
......
libgcc/config/nds32/isr-library/vec_vid31.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.31, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_31
.type _nds32_vector_31, @function
_nds32_vector_31:
......
libgcc/config/nds32/isr-library/vec_vid32.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.32, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_32
.type _nds32_vector_32, @function
_nds32_vector_32:
......
libgcc/config/nds32/isr-library/vec_vid33.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.33, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_33
.type _nds32_vector_33, @function
_nds32_vector_33:
......
libgcc/config/nds32/isr-library/vec_vid34.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.34, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_34
.type _nds32_vector_34, @function
_nds32_vector_34:
......
libgcc/config/nds32/isr-library/vec_vid35.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.35, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_35
.type _nds32_vector_35, @function
_nds32_vector_35:
......
libgcc/config/nds32/isr-library/vec_vid36.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.36, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_36
.type _nds32_vector_36, @function
_nds32_vector_36:
......
libgcc/config/nds32/isr-library/vec_vid37.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.37, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_37
.type _nds32_vector_37, @function
_nds32_vector_37:
......
libgcc/config/nds32/isr-library/vec_vid38.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.38, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_38
.type _nds32_vector_38, @function
_nds32_vector_38:
......
libgcc/config/nds32/isr-library/vec_vid39.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.39, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_39
.type _nds32_vector_39, @function
_nds32_vector_39:
......
libgcc/config/nds32/isr-library/vec_vid40.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.40, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_40
.type _nds32_vector_40, @function
_nds32_vector_40:
......
libgcc/config/nds32/isr-library/vec_vid41.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.41, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_41
.type _nds32_vector_41, @function
_nds32_vector_41:
......
libgcc/config/nds32/isr-library/vec_vid42.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.42, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_42
.type _nds32_vector_42, @function
_nds32_vector_42:
......
libgcc/config/nds32/isr-library/vec_vid43.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.43, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_43
.type _nds32_vector_43, @function
_nds32_vector_43:
......
libgcc/config/nds32/isr-library/vec_vid44.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.44, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_44
.type _nds32_vector_44, @function
_nds32_vector_44:
......
libgcc/config/nds32/isr-library/vec_vid45.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.45, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_45
.type _nds32_vector_45, @function
_nds32_vector_45:
......
libgcc/config/nds32/isr-library/vec_vid46.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.46, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_46
.type _nds32_vector_46, @function
_nds32_vector_46:
......
libgcc/config/nds32/isr-library/vec_vid47.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.47, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_47
.type _nds32_vector_47, @function
_nds32_vector_47:
......
libgcc/config/nds32/isr-library/vec_vid48.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.48, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_48
.type _nds32_vector_48, @function
_nds32_vector_48:
......
libgcc/config/nds32/isr-library/vec_vid49.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.49, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_49
.type _nds32_vector_49, @function
_nds32_vector_49:
......
libgcc/config/nds32/isr-library/vec_vid50.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.50, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_50
.type _nds32_vector_50, @function
_nds32_vector_50:
......
libgcc/config/nds32/isr-library/vec_vid51.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.51, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_51
.type _nds32_vector_51, @function
_nds32_vector_51:
......
libgcc/config/nds32/isr-library/vec_vid52.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.52, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_52
.type _nds32_vector_52, @function
_nds32_vector_52:
......
libgcc/config/nds32/isr-library/vec_vid53.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.53, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_53
.type _nds32_vector_53, @function
_nds32_vector_53:
......
libgcc/config/nds32/isr-library/vec_vid54.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.54, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_54
.type _nds32_vector_54, @function
_nds32_vector_54:
......
libgcc/config/nds32/isr-library/vec_vid55.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.55, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_55
.type _nds32_vector_55, @function
_nds32_vector_55:
......
libgcc/config/nds32/isr-library/vec_vid56.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.56, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_56
.type _nds32_vector_56, @function
_nds32_vector_56:
......
libgcc/config/nds32/isr-library/vec_vid57.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.57, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_57
.type _nds32_vector_57, @function
_nds32_vector_57:
......
libgcc/config/nds32/isr-library/vec_vid58.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.58, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_58
.type _nds32_vector_58, @function
_nds32_vector_58:
......
libgcc/config/nds32/isr-library/vec_vid59.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.59, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_59
.type _nds32_vector_59, @function
_nds32_vector_59:
......
libgcc/config/nds32/isr-library/vec_vid60.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.60, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_60
.type _nds32_vector_60, @function
_nds32_vector_60:
......
libgcc/config/nds32/isr-library/vec_vid61.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.61, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_61
.type _nds32_vector_61, @function
_nds32_vector_61:
......
libgcc/config/nds32/isr-library/vec_vid62.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.62, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_62
.type _nds32_vector_62, @function
_nds32_vector_62:
......
libgcc/config/nds32/isr-library/vec_vid63.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.63, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_63
.type _nds32_vector_63, @function
_nds32_vector_63:
......
libgcc/config/nds32/isr-library/vec_vid64.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.64, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_64
.type _nds32_vector_64, @function
_nds32_vector_64:
......
libgcc/config/nds32/isr-library/vec_vid65.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.65, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_65
.type _nds32_vector_65, @function
_nds32_vector_65:
......
libgcc/config/nds32/isr-library/vec_vid66.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.66, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_66
.type _nds32_vector_66, @function
_nds32_vector_66:
......
libgcc/config/nds32/isr-library/vec_vid67.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.67, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_67
.type _nds32_vector_67, @function
_nds32_vector_67:
......
libgcc/config/nds32/isr-library/vec_vid68.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.68, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_68
.type _nds32_vector_68, @function
_nds32_vector_68:
......
libgcc/config/nds32/isr-library/vec_vid69.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.69, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_69
.type _nds32_vector_69, @function
_nds32_vector_69:
......
libgcc/config/nds32/isr-library/vec_vid70.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.70, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_70
.type _nds32_vector_70, @function
_nds32_vector_70:
......
libgcc/config/nds32/isr-library/vec_vid71.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.71, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_71
.type _nds32_vector_71, @function
_nds32_vector_71:
......
libgcc/config/nds32/isr-library/vec_vid72.S
......@@ -24,8 +24,15 @@
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.72, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_72
.type _nds32_vector_72, @function
_nds32_vector_72:
......
libgcc/config/nds32/t-nds32-isr
......@@ -23,11 +23,11 @@
# Makfile fragment rules for libnds32_isr.a to support ISR attribute extension
###############################################################################
# basic flags setting
# Basic flags setting.
ISR_CFLAGS = $(CFLAGS) -c
# the object files we would like to create
LIBNDS32_ISR_16B_OBJS = \
# The object files we would like to create.
LIBNDS32_ISR_VEC_OBJS = \
vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \
vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \
vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \
......@@ -46,40 +46,9 @@ LIBNDS32_ISR_16B_OBJS = \
vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \
vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \
vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \
vec_vid72.o \
excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \
excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \
intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \
intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \
reset.o
LIBNDS32_ISR_4B_OBJS = \
vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \
vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \
vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \
vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \
vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \
vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \
vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \
vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \
vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \
vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \
vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \
vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \
vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \
vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \
vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \
vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \
vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \
vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \
vec_vid72_4b.o \
excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \
excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \
intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \
intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \
reset_4b.o
vec_vid72.o
LIBNDS32_ISR_COMMON_OBJS = \
LIBNDS32_ISR_JMP_OBJS = \
jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \
jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \
jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \
......@@ -98,29 +67,32 @@ LIBNDS32_ISR_COMMON_OBJS = \
jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \
jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \
jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \
jmptbl_vid72.o \
jmptbl_vid72.o
LIBNDS32_ISR_COMMON_OBJS = \
excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \
excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \
intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \
intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \
reset.o \
nmih.o \
wrh.o
LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS)
LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_VEC_OBJS) $(LIBNDS32_ISR_JMP_OBJS) $(LIBNDS32_ISR_COMMON_OBJS)
# Build common objects for ISR library
nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o
wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o
jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S
# Build vector vid objects for ISR library.
vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
# Build 16b version objects for ISR library. (no "_4b" postfix string)
vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S
# Build jump table objects for ISR library.
jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
# Build commen objects for ISR library.
excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o
......@@ -160,48 +132,12 @@ intr_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
reset.o: $(srcdir)/config/nds32/isr-library/reset.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o
# Build 4b version objects for ISR library.
vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o
excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o
excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o
excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o
excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o
excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o
intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o
intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o
intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o
intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o
intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o
nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o
intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o
wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o
reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S
$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o
# The rule to create libnds32_isr.a file
......
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