Skip to content

R
riscv-gcc-1
Commit a32e5e93 by Richard Henderson Committed by Richard Henderson
Options

libitm: PowerPC support. 

	* configure.tgt: Support powerpc-linux and powerpc-darwin.
	* config/linux/powerpc/futex_bits.h: New file.
	* config/powerpc/cacheline.h: New file.
	* config/powerpc/sjlj.S: New file.
	* config/powerpc/target.h: New file.
	* config/generic/asmcfi.h (cfi_offset): New.
	(cfi_restore, cfi_undefined): New.

From-SVN: r182930
parent 003e0ad6
Showing with 590 additions and 4 deletions
libitm/ChangeLog
2012-01-06 Richard Henderson <rth@redhat.com>
* configure.tgt: Support powerpc-linux and powerpc-darwin.
* config/linux/powerpc/futex_bits.h: New file.
* config/powerpc/cacheline.h: New file.
* config/powerpc/sjlj.S: New file.
* config/powerpc/target.h: New file.
* config/generic/asmcfi.h (cfi_offset): New.
(cfi_restore, cfi_undefined): New.
2012-01-05 Aldy Hernandez <aldyh@redhat.com>
PR other/51171
......
libitm/config/generic/asmcfi.h
/* Copyright (C) 2011 Free Software Foundation, Inc.
/* Copyright (C) 2011, 2012 Free Software Foundation, Inc.
Contributed by Richard Henderson <rth@redhat.com>.
This file is part of the GNU Transactional Memory Library (libitm).
......@@ -34,6 +33,9 @@
#define cfi_def_cfa(r,n) .cfi_def_cfa r, n
#define cfi_rel_offset(r,o) .cfi_rel_offset r, o
#define cfi_register(o,n) .cfi_register o, n
#define cfi_offset(r,o) .cfi_offset r, o
#define cfi_restore(r) .cfi_restore r
#define cfi_undefined(r) .cfi_undefined r
#else
......@@ -44,5 +46,8 @@
#define cfi_def_cfa(r,n)
#define cfi_rel_offset(r,o)
#define cfi_register(o,n)
#define cfi_offset(r,o)
#define cfi_restore(r)
#define cfi_undefined(r)
#endif /* HAVE_AS_CFI_PSEUDO_OP */
libitm/config/linux/powerpc/futex_bits.h 0 → 100644
/* Copyright (C) 2012 Free Software Foundation, Inc.
Contributed by Richard Henderson <rth@redhat.com>.
This file is part of the GNU Transactional Memory Library (libitm).
Libitm is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include <sys/syscall.h>
static inline long
sys_futex0 (std::atomic<int> *addr, int op, int val)
{
register long int r0 __asm__ ("r0");
register long int r3 __asm__ ("r3");
register long int r4 __asm__ ("r4");
register long int r5 __asm__ ("r5");
register long int r6 __asm__ ("r6");
r0 = SYS_futex;
r3 = (long) addr;
r4 = op;
r5 = val;
r6 = 0;
/* ??? The powerpc64 sysdep.h file clobbers ctr; the powerpc32 sysdep.h
doesn't. It doesn't much matter for us. In the interest of unity,
go ahead and clobber it always. */
__asm volatile ("sc; mfcr %0"
: "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6)
: "r"(r0), "r"(r3), "r"(r4), "r"(r5), "r"(r6)
: "r7", "r8", "r9", "r10", "r11", "r12",
"cr0", "ctr", "memory");
if (__builtin_expect (r0 & (1 << 28), 0))
return r3;
return 0;
}
libitm/config/powerpc/cacheline.h 0 → 100644
/* Copyright (C) 2012 Free Software Foundation, Inc.
Contributed by Richard Henderson <rth@redhat.com>.
This file is part of the GNU Transactional Memory Library (libitm).
Libitm is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef LIBITM_POWERPC_CACHELINE_H
#define LIBITM_POWERPC_CACHELINE_H 1
// A cacheline is the smallest unit with which locks are associated.
// The current implementation of the _ITM_[RW] barriers assumes that
// all data types can fit (aligned) within a cachline, which means
// in practice sizeof(complex long double) is the smallest cacheline size.
// It ought to be small enough for efficient manipulation of the
// modification mask, below.
#if defined (__powerpc64__) || defined (__ppc64__)
# define CACHELINE_SIZE 64
#else
# define CACHELINE_SIZE 32
#endif
#include "config/generic/cacheline.h"
#endif // LIBITM_POWERPC_CACHELINE_H
libitm/config/powerpc/target.h 0 → 100644
/* Copyright (C) 2012 Free Software Foundation, Inc.
Contributed by Richard Henderson <rth@redhat.com>.
This file is part of the GNU Transactional Memory Library (libitm).
Libitm is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
namespace GTM HIDDEN {
typedef int v128 __attribute__((vector_size(16), may_alias, aligned(16)));
typedef struct gtm_jmpbuf
{
#if defined(__ALTIVEC__) || defined(__VSX__)
v128 vr[12]; /* vr20-vr31 */
unsigned long long vscr; /* long long for padding only */
#endif
#ifndef _SOFT_FLOAT
double fr[18]; /* f14-f31 */
double fpscr;
#endif
unsigned long gr[18]; /* r14-r31 */
void *cfa;
unsigned long pc;
unsigned long toc; /* r2 on aix, r13 on darwin */
unsigned long cr;
} gtm_jmpbuf;
/* The size of one line in hardware caches (in bytes). */
#if defined (__powerpc64__) || defined (__ppc64__)
# define HW_CACHELINE_SIZE 128
#else
# define HW_CACHELINE_SIZE 32
#endif
static inline void
cpu_relax (void)
{
__asm volatile ("" : : : "memory");
}
} // namespace GTM
libitm/configure.tgt
# -*- shell-script -*-
# Copyright (C) 2011 Free Software Foundation, Inc.
# Copyright (C) 2011, 2012 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
......@@ -46,7 +46,8 @@ fi
# Map the target cpu to an ARCH sub-directory. At the same time,
# work out any special compilation flags as necessary.
case "${target_cpu}" in
alpha*) ARCH=alpha ;;
alpha*) ARCH=alpha ;;
rs6000 | powerpc*) ARCH=powerpc ;;
arm*) ARCH=arm ;;
......@@ -94,6 +95,11 @@ case "${target}" in
fi
;;
powerpc*-*-aix* | rs6000-*-aix*)
# The system ought to be supported, but sjlj.S has not been ported.
UNSUPPORTED=1
;;
*-*-gnu* | *-*-k*bsd*-gnu \
| *-*-netbsd* | *-*-freebsd* | *-*-openbsd* \
| *-*-solaris2* | *-*-sysv4* | *-*-irix6* | *-*-osf* | *-*-hpux11* \
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment