mips-protos.h (mips_emit_binary): Declare.

gcc/
	* config/mips/mips-protos.h (mips_emit_binary): Declare.
	* config/mips/mips.c (mips_emit_binary): Make global.
	(mips_set_mips16_mode): Turn off -mfix-r4000 in MIPS16 mode.
	(mips_conditional_register_usage): Don't treat LO and HI as
	register operands in MIPS16 mode.
	(mips_mulsidi3_gen_fn): Use {u,}mulsidi3_{32,64}bit_mips16
	for MIPS16 code.
	* config/mips/predicates.md (muldiv_target_operand): New predicate.
	(move_operand): Allow hilo_operand.
	* config/mips/mips.md (mul<mode>3): Explicitly specify LO as the
	target of MIPS16 multiplies, then move it into the target register.
	(mul<mode>3_internal, *macc2, *msac2): Use muldiv_target_operand.
	(<u>mulsidi3_32bit_mips16): New expander.
	(<u>mulsidi3_32bit): Use muldiv_target_operand.
	(<u>mulsidi3_32bit_r4000): Disable for ISA_HAS_DSP.
	(<u>mulsidi3_64bit): Require !TARGET_MIPS16.  Split into
	<u>mulsidi3_64bit_split.
	(<u>mulsidi3_64bit_mips16): New expander.
	(<u>mulsidi3_64bit_split): Likewise, using expansions from
	two previous define_splits.
	(<u>mulsidi3_64bit_hilo, *muls<u>_di, <u>msubsidi4): Use
	muldiv_target_operand.
	(<su>mulsi3_highpart): Use <su>mulsi3_highpart_split for MIPS16 code.
	(<su>mulsi3_highpart_internal): Require !TARGET_MIPS16.
	Split into <su>mulsi3_highpart_split.
	(<su>mulsi3_highpart_split): New expander.
	(<su>muldi3_highpart): Turn into a define_expand.
	Use <su>muldi3_highpart_split for MIPS16 code.
	(<su>muldi3_highpart_internal): Renamed from <su>muldi3_highpart.
	Require !TARGET_MIPS16.  Split into <su>muldi3_highpart_split.
	(<su>muldi3_highpart_split): New expander.
	(<u>mulditi3): Explicitly specify LO as the target of MIPS16
	multiplies, then move it into the target register.
	(<u>mulditi3_internal, <u>maddsidi4): Use muldiv_target_operand.
	(divmod<mode>4, udivmod<mode>4): Turn into define_expands.
	Use <u>divmod<mode>4_split for MIPS16 code, then explicitly
	move LO into operand 0.
	(divmod<mode>4_internal, udivmod<mode>4_internal): Renamed
	from <u>divmod<mode>4.  Use muldiv_target_operand.
	Require !TARGET_MIPS16.  Split into <u>divmod<mode>4_split.
	(<u>divmod<mode>4_split): New expander.
	(<u>divmod<GPR:mode>4_hilo_<HILO:mode>): Use muldiv_target_operand.
	(mfhi<GPR:mode>_<HILO:mode>): Use hilo_operand.

gcc/testsuite/
	* gcc.target/mips/mult-2.c, gcc.target/mips/mult-3.c,
	gcc.target/mips/mult-4.c, gcc.target/mips/mult-5.c,
	gcc.target/mips/mult-6.c, gcc.target/mips/mult-7.c,
	gcc.target/mips/mult-8.c, gcc.target/mips/mult-9.c,
	gcc.target/mips/mult-10.c, gcc.target/mips/mult-11.c,
	gcc.target/mips/mult-12.c, gcc.target/mips/mult-13.c,
	gcc.target/mips/mult-14.c, gcc.target/mips/mult-15.c,
	gcc.target/mips/mult-16.c, gcc.target/mips/mult-17.c,
	gcc.target/mips/mult-18.c, gcc.target/mips/mult-19.c,
	gcc.target/mips/div-1.c, gcc.target/mips/div-2.c,
	gcc.target/mips/div-3.c, gcc.target/mips/div-4.c,
	gcc.target/mips/div-5.c, gcc.target/mips/div-6.c,
	gcc.target/mips/div-7.c, gcc.target/mips/div-8.c,
	gcc.target/mips/div-9.c, gcc.target/mips/div-10.c,
	gcc.target/mips/div-11.c, gcc.target/mips/div-12.c: New tests.
	* gcc.target/mips/fix-r4000-1.c (foo, bar): Add NOMIPS16.
	* gcc.target/mips/fix-r4000-2.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-3.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-4.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-5.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-6.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-7.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-8.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-9.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-10.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-11.c (foo): Likewise.
	* gcc.target/mips/fix-r4000-12.c (foo): Likewise.

From-SVN: r181761

gcc/ChangeLog

 2011-11-27  Richard Sandiford  <rdsandiford@googlemail.com>
 
+	* config/mips/mips-protos.h (mips_emit_binary): Declare.
+	* config/mips/mips.c (mips_emit_binary): Make global.
+	(mips_set_mips16_mode): Turn off -mfix-r4000 in MIPS16 mode.
+	(mips_conditional_register_usage): Don't treat LO and HI as
+	register operands in MIPS16 mode.
+	(mips_mulsidi3_gen_fn): Use {u,}mulsidi3_{32,64}bit_mips16
+	for MIPS16 code.
+	* config/mips/predicates.md (muldiv_target_operand): New predicate.
+	(move_operand): Allow hilo_operand.
+	* config/mips/mips.md (mul<mode>3): Explicitly specify LO as the
+	target of MIPS16 multiplies, then move it into the target register.
+	(mul<mode>3_internal, *macc2, *msac2): Use muldiv_target_operand.
+	(<u>mulsidi3_32bit_mips16): New expander.
+	(<u>mulsidi3_32bit): Use muldiv_target_operand.
+	(<u>mulsidi3_32bit_r4000): Disable for ISA_HAS_DSP.
+	(<u>mulsidi3_64bit): Require !TARGET_MIPS16.  Split into
+	<u>mulsidi3_64bit_split.
+	(<u>mulsidi3_64bit_mips16): New expander.
+	(<u>mulsidi3_64bit_split): Likewise, using expansions from
+	two previous define_splits.
+	(<u>mulsidi3_64bit_hilo, *muls<u>_di, <u>msubsidi4): Use
+	muldiv_target_operand.
+	(<su>mulsi3_highpart): Use <su>mulsi3_highpart_split for MIPS16 code.
+	(<su>mulsi3_highpart_internal): Require !TARGET_MIPS16.
+	Split into <su>mulsi3_highpart_split.
+	(<su>mulsi3_highpart_split): New expander.
+	(<su>muldi3_highpart): Turn into a define_expand.
+	Use <su>muldi3_highpart_split for MIPS16 code.
+	(<su>muldi3_highpart_internal): Renamed from <su>muldi3_highpart.
+	Require !TARGET_MIPS16.  Split into <su>muldi3_highpart_split.
+	(<su>muldi3_highpart_split): New expander.
+	(<u>mulditi3): Explicitly specify LO as the target of MIPS16
+	multiplies, then move it into the target register.
+	(<u>mulditi3_internal, <u>maddsidi4): Use muldiv_target_operand.
+	(divmod<mode>4, udivmod<mode>4): Turn into define_expands.
+	Use <u>divmod<mode>4_split for MIPS16 code, then explicitly
+	move LO into operand 0.
+	(divmod<mode>4_internal, udivmod<mode>4_internal): Renamed
+	from <u>divmod<mode>4.  Use muldiv_target_operand.
+	Require !TARGET_MIPS16.  Split into <u>divmod<mode>4_split.
+	(<u>divmod<mode>4_split): New expander.
+	(<u>divmod<GPR:mode>4_hilo_<HILO:mode>): Use muldiv_target_operand.
+	(mfhi<GPR:mode>_<HILO:mode>): Use hilo_operand.
+
+2011-11-27  Richard Sandiford  <rdsandiford@googlemail.com>
+
 	* hard-reg-set.h (target_hard_regs): Add x_accessible_reg_set
 	and x_operand_reg_set.
 	(accessible_reg_set, operand_reg_set): New macros.

gcc/config/mips/mips-protos.h

@@ -191,6 +191,9 @@ extern int mips_split_const_insns (rtx);
 extern int mips_load_store_insns (rtx, rtx);
 extern int mips_idiv_insns (void);
 extern rtx mips_emit_move (rtx, rtx);
+#ifdef RTX_CODE
+extern void mips_emit_binary (enum rtx_code, rtx, rtx, rtx);
+#endif
 extern rtx mips_pic_base_register (rtx);
 extern rtx mips_got_load (rtx, rtx, enum mips_symbol_type);
 extern bool mips_split_symbol (rtx, rtx, enum machine_mode, rtx *);

gcc/config/mips/mips.c

@@ -2398,7 +2398,7 @@ mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
 
 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)).  */
 
-static void
+void
 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
 {
   emit_insn (gen_rtx_SET (VOIDmode, target,
@@ -15250,6 +15250,11 @@ mips_set_mips16_mode (int mips16_p)
       /* MIPS16 has no BAL instruction.  */
       target_flags &= ~MASK_RELAX_PIC_CALLS;
 
+      /* The R4000 errata don't apply to any known MIPS16 cores.
+	 It's simpler to make the R4000 fixes and MIPS16 mode
+	 mutually exclusive.  */
+      target_flags &= ~MASK_FIX_R4000;
+
       if (flag_pic && !TARGET_OLDABI)
 	sorry ("MIPS16 PIC for ABIs other than o32 and o64");
 
@@ -15856,12 +15861,12 @@ mips_conditional_register_usage (void)
       SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
       fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
     }
-  /* In MIPS16 mode, we permit the $t temporary registers to be used
-     for reload.  We prohibit the unused $s registers, since they
-     are call-saved, and saving them via a MIPS16 register would
-     probably waste more time than just reloading the value.  */
   if (TARGET_MIPS16)
     {
+      /* In MIPS16 mode, we permit the $t temporary registers to be used
+	 for reload.  We prohibit the unused $s registers, since they
+	 are call-saved, and saving them via a MIPS16 register would
+	 probably waste more time than just reloading the value.  */
       fixed_regs[18] = call_used_regs[18] = 1;
       fixed_regs[19] = call_used_regs[19] = 1;
       fixed_regs[20] = call_used_regs[20] = 1;
@@ -15871,6 +15876,12 @@ mips_conditional_register_usage (void)
       fixed_regs[26] = call_used_regs[26] = 1;
       fixed_regs[27] = call_used_regs[27] = 1;
       fixed_regs[30] = call_used_regs[30] = 1;
+
+      /* Do not allow HI and LO to be treated as register operands.
+	 There are no MTHI or MTLO instructions (or any real need
+	 for them) and one-way registers cannot easily be reloaded.  */
+      AND_COMPL_HARD_REG_SET (operand_reg_set,
+			      reg_class_contents[(int) MD_REGS]);
     }
   /* $f20-$f23 are call-clobbered for n64.  */
   if (mips_abi == ABI_64)
@@ -16056,12 +16067,20 @@ mips_mulsidi3_gen_fn (enum rtx_code ext_code)
 	 case we still expand mulsidi3 for DMUL.  */
       if (ISA_HAS_DMUL3)
 	return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
+      if (TARGET_MIPS16)
+	return (signed_p
+		? gen_mulsidi3_64bit_mips16
+		: gen_umulsidi3_64bit_mips16);
       if (TARGET_FIX_R4000)
 	return NULL;
       return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
     }
   else
     {
+      if (TARGET_MIPS16)
+	return (signed_p
+		? gen_mulsidi3_32bit_mips16
+		: gen_umulsidi3_32bit_mips16);
       if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
 	return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
       return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;

gcc/config/mips/predicates.md

@@ -127,6 +127,11 @@
   (and (match_code "reg,subreg")
        (match_test "ST_REG_P (true_regnum (op))")))
 
+(define_predicate "muldiv_target_operand"
+  (if_then_else (match_test "TARGET_MIPS16")
+		(match_operand 0 "hilo_operand")
+		(match_operand 0 "register_operand")))
+
 (define_special_predicate "pc_or_label_operand"
   (match_code "pc,label_ref"))
 
@@ -189,7 +194,9 @@
 })
 
 (define_predicate "move_operand"
-  (match_operand 0 "general_operand")
+  ;; Allow HI and LO to be used as the source of a MIPS16 move.
+  (ior (match_operand 0 "general_operand")
+       (match_operand 0 "hilo_operand"))
 {
   enum mips_symbol_type symbol_type;
 

gcc/testsuite/ChangeLog

 2011-11-27  Richard Sandiford  <rdsandiford@googlemail.com>
 
+	* gcc.target/mips/mult-2.c, gcc.target/mips/mult-3.c,
+	gcc.target/mips/mult-4.c, gcc.target/mips/mult-5.c,
+	gcc.target/mips/mult-6.c, gcc.target/mips/mult-7.c,
+	gcc.target/mips/mult-8.c, gcc.target/mips/mult-9.c,
+	gcc.target/mips/mult-10.c, gcc.target/mips/mult-11.c,
+	gcc.target/mips/mult-12.c, gcc.target/mips/mult-13.c,
+	gcc.target/mips/mult-14.c, gcc.target/mips/mult-15.c,
+	gcc.target/mips/mult-16.c, gcc.target/mips/mult-17.c,
+	gcc.target/mips/mult-18.c, gcc.target/mips/mult-19.c,
+	gcc.target/mips/div-1.c, gcc.target/mips/div-2.c,
+	gcc.target/mips/div-3.c, gcc.target/mips/div-4.c,
+	gcc.target/mips/div-5.c, gcc.target/mips/div-6.c,
+	gcc.target/mips/div-7.c, gcc.target/mips/div-8.c,
+	gcc.target/mips/div-9.c, gcc.target/mips/div-10.c,
+	gcc.target/mips/div-11.c, gcc.target/mips/div-12.c: New tests.
+	* gcc.target/mips/fix-r4000-1.c (foo, bar): Add NOMIPS16.
+	* gcc.target/mips/fix-r4000-2.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-3.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-4.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-5.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-6.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-7.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-8.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-9.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-10.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-11.c (foo): Likewise.
+	* gcc.target/mips/fix-r4000-12.c (foo): Likewise.
+
+2011-11-27  Richard Sandiford  <rdsandiford@googlemail.com>
+
 	* gcc.target/mips/mips.exp (mips-dg-options): Make -mno-dsp
 	imply -mno-dspr2.
 	* gcc.target/mips/no-dsp-1.c: New test.

gcc/testsuite/gcc.target/mips/div-1.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tddiv\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x / y;
+}

gcc/testsuite/gcc.target/mips/div-10.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdivu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x / y;
+}

gcc/testsuite/gcc.target/mips/div-11.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdiv\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x % y;
+}

gcc/testsuite/gcc.target/mips/div-12.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdivu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x % y;
+}

gcc/testsuite/gcc.target/mips/div-2.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tddivu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x / y;
+}

gcc/testsuite/gcc.target/mips/div-3.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tddiv\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x % y;
+}

gcc/testsuite/gcc.target/mips/div-4.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tddivu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x % y;
+}

gcc/testsuite/gcc.target/mips/div-5.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdiv\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x / y;
+}

gcc/testsuite/gcc.target/mips/div-6.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdivu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x / y;
+}

gcc/testsuite/gcc.target/mips/div-7.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdiv\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x % y;
+}

gcc/testsuite/gcc.target/mips/div-8.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdivu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x % y;
+}

gcc/testsuite/gcc.target/mips/div-9.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdiv\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x / y;
+}

gcc/testsuite/gcc.target/mips/fix-r4000-1.c

 /* { dg-options "-march=r4000 -mfix-r4000 -O2 -dp" } */
 typedef int int32_t;
 typedef int uint32_t;
-int32_t foo (int32_t x, int32_t y) { return x * y; }
-uint32_t bar (uint32_t x, uint32_t y) { return x * y; }
+NOMIPS16 int32_t foo (int32_t x, int32_t y) { return x * y; }
+NOMIPS16 uint32_t bar (uint32_t x, uint32_t y) { return x * y; }
 /* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */

gcc/testsuite/gcc.target/mips/fix-r4000-10.c

@@ -4,5 +4,5 @@
 /* { dg-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */
 typedef unsigned long long uint64_t;
 typedef unsigned int uint128_t __attribute__((mode(TI)));
-uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; }
+NOMIPS16 uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; }
 /* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-11.c

 /* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */
 typedef long long int64_t;
-int64_t foo (int64_t x) { return x / 11993; }
+NOMIPS16 int64_t foo (int64_t x) { return x / 11993; }
 /* { dg-final { scan-assembler "[concat {\tdmult\t\$4,\$[0-9]+[^\n]+smuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-12.c

 /* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */
 typedef unsigned long long uint64_t;
-uint64_t foo (uint64_t x) { return x / 11993; }
+NOMIPS16 uint64_t foo (uint64_t x) { return x / 11993; }
 /* { dg-final { scan-assembler "[concat {\tdmultu\t\$4,\$[0-9]+[^\n]+umuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-2.c

 /* { dg-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */
 typedef int int32_t;
 typedef long long int64_t;
-int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; }
+NOMIPS16 int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; }
 /* ??? A highpart pattern would be a better choice, but we currently
    don't use them.  */
 /* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-3.c

 /* { dg-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */
 typedef unsigned int uint32_t;
 typedef unsigned long long uint64_t;
-uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; }
+NOMIPS16 uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; }
 /* ??? A highpart pattern would be a better choice, but we currently
    don't use them.  */
 /* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-4.c

@@ -4,5 +4,5 @@
 /* { dg-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */
 typedef int int32_t;
 typedef long long int64_t;
-int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; }
+NOMIPS16 int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; }
 /* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-5.c

@@ -4,5 +4,5 @@
 /* { dg-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */
 typedef unsigned int uint32_t;
 typedef unsigned long long uint64_t;
-uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; }
+NOMIPS16 uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; }
 /* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-6.c

 /* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */
 typedef long long int64_t;
 typedef unsigned long long uint64_t;
-int64_t foo (int64_t x, int64_t y) { return x * y; }
-uint64_t bar (uint64_t x, uint64_t y) { return x * y; }
+NOMIPS16 int64_t foo (int64_t x, int64_t y) { return x * y; }
+NOMIPS16 uint64_t bar (uint64_t x, uint64_t y) { return x * y; }
 /* { dg-final { scan-assembler-times "[concat {\tdmult\t\$[45],\$[45][^\n]+muldi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */

gcc/testsuite/gcc.target/mips/fix-r4000-7.c

 /* { dg-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */
 typedef long long int64_t;
 typedef int int128_t __attribute__((mode(TI)));
-int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; }
+NOMIPS16 int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; }
 /* ??? A highpart pattern would be a better choice, but we currently
    don't use them.  */
 /* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-8.c

 /* { dg-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */
 typedef unsigned long long uint64_t;
 typedef unsigned int uint128_t __attribute__((mode(TI)));
-uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; }
+NOMIPS16 uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; }
 /* ??? A highpart pattern would be a better choice, but we currently
    don't use them.  */
 /* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */

gcc/testsuite/gcc.target/mips/fix-r4000-9.c

@@ -4,5 +4,5 @@
 /* { dg-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */
 typedef long long int64_t;
 typedef int int128_t __attribute__((mode(TI)));
-int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; }
+NOMIPS16 int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; }
 /* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */

gcc/testsuite/gcc.target/mips/mult-10.c

+/* { dg-options "-O2 -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}

gcc/testsuite/gcc.target/mips/mult-11.c

+/* { dg-options "-O2 -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}

gcc/testsuite/gcc.target/mips/mult-12.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x * y;
+}

gcc/testsuite/gcc.target/mips/mult-13.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x * y;
+}

gcc/testsuite/gcc.target/mips/mult-14.c

+/* { dg-options "-O -mgp32 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tdsll\t" } } */
+/* { dg-final { scan-assembler-not "\tdsrl\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 DI
+f (SI x, SI y)
+{
+  return (DI) x * y;
+}

gcc/testsuite/gcc.target/mips/mult-15.c

+/* { dg-options "-O -mgp32 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tdsll\t" } } */
+/* { dg-final { scan-assembler-not "\tdsrl\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 DI
+f (SI x, SI y)
+{
+  return (DI) x * y;
+}

gcc/testsuite/gcc.target/mips/mult-16.c

+/* { dg-options "-O2 -mgp32 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}

gcc/testsuite/gcc.target/mips/mult-17.c

+/* { dg-options "-O -mgp32 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}

gcc/testsuite/gcc.target/mips/mult-18.c

+/* { dg-options "-O -mgp32 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x * y;
+}

gcc/testsuite/gcc.target/mips/mult-19.c

+/* { dg-options "-O -mgp32 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x * y;
+}

gcc/testsuite/gcc.target/mips/mult-2.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdmult\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+
+typedef int TI __attribute__((mode(TI)));
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 TI
+f (DI x, DI y)
+{
+  return (TI) x * y;
+}

gcc/testsuite/gcc.target/mips/mult-3.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdmultu\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+
+typedef unsigned int TI __attribute__((mode(TI)));
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 TI
+f (DI x, DI y)
+{
+  return (TI) x * y;
+}

gcc/testsuite/gcc.target/mips/mult-4.c

+/* { dg-options "-O2 -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdmult\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+typedef int TI __attribute__((mode(TI)));
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return ((TI) x * y) >> 64;
+}

gcc/testsuite/gcc.target/mips/mult-5.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdmultu\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+typedef unsigned int TI __attribute__((mode(TI)));
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return ((TI) x * y) >> 64;
+}

gcc/testsuite/gcc.target/mips/mult-6.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x * y;
+}

gcc/testsuite/gcc.target/mips/mult-7.c

+/* { dg-options "-O -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x * y;
+}

gcc/testsuite/gcc.target/mips/mult-8.c

+/* { dg-options "-O2 -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */
+/* { dg-final { scan-assembler "\tdsrl\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 DI
+f (SI x, SI y)
+{
+  return (DI) x * y;
+}

gcc/testsuite/gcc.target/mips/mult-9.c

+/* { dg-options "-O2 -mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */
+/* { dg-final { scan-assembler "\tdsrl\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 DI
+f (SI x, SI y)
+{
+  return (DI) x * y;
+}