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Commit a27fb29b by Richard Sandiford Committed by Richard Sandiford
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invoke.texi: Document -mabi=meabi, and expand on the EABI description. 

	* doc/invoke.texi: Document -mabi=meabi, and expand on the EABI
	description.  Document -mips32, -mips64, and the associated -march
	values.  Describe the "mipsN" arguments to -march.  Say that the
	-mipsN options are equivalent to -march.  Reword the description
	of default type sizes.
	* toplev.h (target_flags_explicit): Declare.
	* toplev.c (target_flags_explicit): New var.
	(set_target_switch): Update target_flags_explicit.
	* config/mips/abi64.h (SUBTARGET_TARGET_OPTIONS): Undefine.
	* config/mips/elf64.h (MIPS_ISA_DEFAULT): Undefine.
	* config/mips/iris6.h (SUBTARGET_ASM_SPEC): -mabi=64 implies -mips3.
	* config/mips/isa3264.h (MIPS_ENABLE_EMBEDDED_O32): Undefine.
	* config/mips/mips.h (mips_cpu_info): New struct.
	(mips_cpu_string, mips_explicit_type_size_string): Remove.
	(mips_cpu_info_table, mips_arch_info, mips_tune_info): Declare.
	(MIPS_CPP_SET_PROCESSOR): New macro.
	(TARGET_CPP_BUILTINS): Declare a macro for each supported processor.
	Define _MIPS_ARCH and _MIPS_TUNE.
	(MIPS_ISA_DEFAULT): Don't provide a default value.  Instead...
	(MIPS_CPU_STRING_DEFAULT): Set to "from-abi" if neither it nor
	MIPS_ISA_DEFAULT were already defined.
	(MULTILIB_DEFAULTS): Add MULTILIB_ABI_DEFAULT.
	(TARGET_OPTIONS): Remove -mcpu and -mexplicit-type-size.
	(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New.
	(GAS_ASM_SPEC): Remove -march, -mcpu, -mgp* and -mabi rules.
	(ABI_GAS_ASM_SPEC): Remove.
	(MULTILIB_ABI_DEFAULT, ASM_ABI_DEFAULT_SPEC): New macros.
	(ASM_SPEC): Add -mgp32, -mgp64, -march, -mabi=eabi and -mabi=o64.
	Invoke %(asm_abi_default_spec) if no ABI was specified.
	(CC1_SPEC): Remove ISA -> register-size rules.
	(EXTRA_SPECS): Remove abi_gas_asm_spec.  Add asm_abi_default_spec.
	* config/mips/mips.c (mips_arch_info, mips_tune_info): New vars.
	(mips_cpu_string, mips_explicit_type_size_string): Remove.
	(mips_cpu_info_table): New array.
	(mips_set_architecture, mips_set_tune): New fns.
	(override_options): Rework to make -mipsN equivalent to -march.
	Detect more erroneous cases, including those removed from CC1_SPEC.
	Don't change the ABI based on architecture, or vice versa.
	Unify logic with GAS.
	(mips_asm_file_start): Get architecture name from mips_arch_info.
	(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
	(mips_parse_cpu): Take the name of the option as argument.  Handle
	'from-abi'.  Raise an error if the option is wrong.
	(mips_cpu_info_from_isa): New fn.

[gcc/testsuite]
	* gcc.dg/mips-args-[123].c: New tests.

From-SVN: r55747
parent 6bbdc759
Showing with 340 additions and 100 deletions
gcc/ChangeLog
2002-07-25 Richard Sandiford <rsandifo@redhat.com>
* doc/invoke.texi: Document -mabi=meabi, and expand on the EABI
description. Document -mips32, -mips64, and the associated -march
values. Describe the "mipsN" arguments to -march. Say that the
-mipsN options are equivalent to -march. Reword the description
of default type sizes.
* toplev.h (target_flags_explicit): Declare.
* toplev.c (target_flags_explicit): New var.
(set_target_switch): Update target_flags_explicit.
* config/mips/abi64.h (SUBTARGET_TARGET_OPTIONS): Undefine.
* config/mips/elf64.h (MIPS_ISA_DEFAULT): Undefine.
* config/mips/iris6.h (SUBTARGET_ASM_SPEC): -mabi=64 implies -mips3.
* config/mips/isa3264.h (MIPS_ENABLE_EMBEDDED_O32): Undefine.
* config/mips/mips.h (mips_cpu_info): New struct.
(mips_cpu_string, mips_explicit_type_size_string): Remove.
(mips_cpu_info_table, mips_arch_info, mips_tune_info): Declare.
(MIPS_CPP_SET_PROCESSOR): New macro.
(TARGET_CPP_BUILTINS): Declare a macro for each supported processor.
Define _MIPS_ARCH and _MIPS_TUNE.
(MIPS_ISA_DEFAULT): Don't provide a default value. Instead...
(MIPS_CPU_STRING_DEFAULT): Set to "from-abi" if neither it nor
MIPS_ISA_DEFAULT were already defined.
(MULTILIB_DEFAULTS): Add MULTILIB_ABI_DEFAULT.
(TARGET_OPTIONS): Remove -mcpu and -mexplicit-type-size.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New.
(GAS_ASM_SPEC): Remove -march, -mcpu, -mgp* and -mabi rules.
(ABI_GAS_ASM_SPEC): Remove.
(MULTILIB_ABI_DEFAULT, ASM_ABI_DEFAULT_SPEC): New macros.
(ASM_SPEC): Add -mgp32, -mgp64, -march, -mabi=eabi and -mabi=o64.
Invoke %(asm_abi_default_spec) if no ABI was specified.
(CC1_SPEC): Remove ISA -> register-size rules.
(EXTRA_SPECS): Remove abi_gas_asm_spec. Add asm_abi_default_spec.
* config/mips/mips.c (mips_arch_info, mips_tune_info): New vars.
(mips_cpu_string, mips_explicit_type_size_string): Remove.
(mips_cpu_info_table): New array.
(mips_set_architecture, mips_set_tune): New fns.
(override_options): Rework to make -mipsN equivalent to -march.
Detect more erroneous cases, including those removed from CC1_SPEC.
Don't change the ABI based on architecture, or vice versa.
Unify logic with GAS.
(mips_asm_file_start): Get architecture name from mips_arch_info.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): Take the name of the option as argument. Handle
'from-abi'. Raise an error if the option is wrong.
(mips_cpu_info_from_isa): New fn.
2002-07-25 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (tablejump_mips161): Use gen_rtx_LABEL_REF.
(tablejump_mips162): Likewise.
......
gcc/config/mips/abi64.h
......@@ -21,11 +21,6 @@ Boston, MA 02111-1307, USA. */
/* Macros to implement the 64 bit ABI. This file is meant to be included
after mips.h. */
#undef SUBTARGET_TARGET_OPTIONS
#define SUBTARGET_TARGET_OPTIONS \
{ "abi=", &mips_abi_string, \
"Specify ABI to use"},
#undef STACK_BOUNDARY
#define STACK_BOUNDARY \
((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
......
gcc/config/mips/elf64.h
......@@ -22,15 +22,12 @@ Boston, MA 02111-1307, USA. */
#define OBJECT_FORMAT_ELF
/* Default to -mips3. */
/* If an embedded ABI is selected, prefer to generate 64-bit code.
Implies -mips3 in such cases. */
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_FLOAT64|MASK_64BIT
#endif
#ifndef MIPS_ISA_DEFAULT
#define MIPS_ISA_DEFAULT 3
#endif
/* This should change to n32 when it is supported in gas. */
#ifndef MIPS_ABI_DEFAULT
#define MIPS_ABI_DEFAULT ABI_O64
......
gcc/config/mips/iris6.h
......@@ -238,7 +238,7 @@ Boston, MA 02111-1307, USA. */
on the mipsX option. */
/* If no mips[3,4] option given, give the appropriate default for mabi=X */
#undef SUBTARGET_ASM_SPEC
#define SUBTARGET_ASM_SPEC "%{!mabi*:-n32} %{!mips*: %{!mabi*:-mips3} %{mabi=n32:-mips3} %{mabi=64:-mips4}}"
#define SUBTARGET_ASM_SPEC "%{!mabi*:-n32} %{!mips*: %{!mabi*:-mips3} %{mabi=n32|mabi=64:-mips3}}"
/* Must pass -g0 to the assembler, otherwise it may overwrite our
debug info with its own debug info. */
......
gcc/config/mips/isa3264.h
......@@ -27,10 +27,6 @@ Boston, MA 02111-1307, USA. */
#define MIPS_ABI_DEFAULT ABI_MEABI
#endif
#ifndef MIPS_ENABLE_EMBEDDED_O32
#define MIPS_ENABLE_EMBEDDED_O32 1
#endif
#ifndef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
#endif
......
gcc/doc/invoke.texi
......@@ -6976,65 +6976,77 @@ These @samp{-m} options are defined for the MIPS family of computers:
@table @gcctabopt
@item -march=@var{cpu-type}
@item -march=@var{arch}
@opindex march
Assume the defaults for the machine type @var{cpu-type} when generating
instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000},
@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r5000}, @samp{r6000}, @samp{r8000},
and @samp{orion}. Additionally, the @samp{r2000}, @samp{r3000},
@samp{r4000}, @samp{r5000}, and @samp{r6000} can be abbreviated as
@samp{r2k} (or @samp{r2K}), @samp{r3k}, etc.
@item -mtune=@var{cpu-type}
Generate code that will run on @var{arch}, which can be the name of a
generic MIPS ISA, or the name of a particular processor. The ISA names
are: @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4}, @samp{mips32}
and @samp{mips64}. The processor names are: @samp{r2000},
@samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{vr4100}, @samp{vr4300},
@samp{r4400}, @samp{r4600}, @samp{r4650}, @samp{vr5000}, @samp{r6000},
@samp{r8000}, @samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc}
and @samp{orion}. The special value @samp{from-abi} selects the
most compatible architecture for the selected ABI (that is,
@samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
In processor names, a final @samp{000} can be abbreviated as @samp{k}
(for example, @samp{-march=r2k}). Prefixes are optional, and
@samp{vr} may be written @samp{r}.
GCC defines two macros based on the value of this option. The first
is @samp{_MIPS_ARCH}, which gives the name of target architecture, as
a string. The second has the form @samp{_MIPS_ARCH_@var{foo}},
where @var{foo} is the capitialized value of @samp{_MIPS_ARCH}@.
For example, @samp{-march=r2000} will set @samp{_MIPS_ARCH}
to @samp{"r2000"} and define the macro @samp{_MIPS_ARCH_R2000}.
Note that the @samp{_MIPS_ARCH} macro uses the processor names given
above. In other words, it will have the full prefix and will not
abbreviate @samp{000} as @samp{k}. In the case of @samp{from-abi},
the macro names the resolved architecture (either @samp{"mips1"} or
@samp{"mips3"}). It names the default architecture when no
@option{-march} option is given.
@item -mtune=@var{arch}
@opindex mtune
Assume the defaults for the machine type @var{cpu-type} when scheduling
instructions. The choices for @var{cpu-type} are @samp{r2000}, @samp{r3000},
@samp{r3900}, @samp{r4000}, @samp{r4100}, @samp{r4300}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r5000}, @samp{r6000}, @samp{r8000},
and @samp{orion}. Additionally, the @samp{r2000}, @samp{r3000},
@samp{r4000}, @samp{r5000}, and @samp{r6000} can be abbreviated as
@samp{r2k} (or @samp{r2K}), @samp{r3k}, etc. While picking a specific
@var{cpu-type} will schedule things appropriately for that particular
chip, the compiler will not generate any code that does not meet level 1
of the MIPS ISA (instruction set architecture) without a @option{-mipsX}
or @option{-mabi} switch being used.
Optimize for @var{arch}. Among other things, this option controls
the way instructions are scheduled, and the perceived cost of arithmetic
operations. The list of @var{arch} values is the same as for
@option{-march}.
@item -mcpu=@var{cpu-type}
@opindex mcpu
This is identical to specifying both @option{-march} and @option{-mtune}.
When this option is not used, GCC will optimize for the processor
specified by @option{-march}. By using @option{-march} and
@option{-mtune} together, it is possible to generate code that will
run on a family of processors, but optimize the code for one
particular member of that family.
@samp{-mtune} defines the macros @samp{_MIPS_TUNE} and
@samp{_MIPS_TUNE_@var{foo}}, which work in the same way as the
@samp{-march} ones described above.
@item -mips1
@opindex mips1
Issue instructions from level 1 of the MIPS ISA@. This is the default.
@samp{r3000} is the default @var{cpu-type} at this ISA level.
Equivalent to @samp{-march=mips1}.
@item -mips2
@opindex mips2
Issue instructions from level 2 of the MIPS ISA (branch likely, square
root instructions). @samp{r6000} is the default @var{cpu-type} at this
ISA level.
Equivalent to @samp{-march=mips2}.
@item -mips3
@opindex mips3
Issue instructions from level 3 of the MIPS ISA (64-bit instructions).
@samp{r4000} is the default @var{cpu-type} at this ISA level.
Equivalent to @samp{-march=mips3}.
@item -mips4
@opindex mips4
Issue instructions from level 4 of the MIPS ISA (conditional move,
prefetch, enhanced FPU instructions). @samp{r8000} is the default
@var{cpu-type} at this ISA level.
Equivalent to @samp{-march=mips4}.
@item -mfp32
@opindex mfp32
Assume that 32 32-bit floating point registers are available. This is
the default.
@item -mips32
@opindex mips32
Equivalent to @samp{-march=mips32}.
@item -mfp64
@opindex mfp64
Assume that 32 64-bit floating point registers are available. This is
the default when the @option{-mips3} option is used.
@item -mips64
@opindex mips64
Equivalent to @samp{-march=mips64}.
@item -mfused-madd
@itemx -mno-fused-madd
......@@ -7048,15 +7060,21 @@ in the mode where denormals are rounded to zero where denormals
generated by multiply and accumulate instructions cause exceptions
anyway.
@item -mfp32
@opindex mfp32
Assume that floating point registers are 32 bits wide.
@item -mfp64
@opindex mfp64
Assume that floating point registers are 64 bits wide.
@item -mgp32
@opindex mgp32
Assume that 32 32-bit general purpose registers are available. This is
the default.
Assume that general purpose registers are 32 bits wide.
@item -mgp64
@opindex mgp64
Assume that 32 64-bit general purpose registers are available. This is
the default when the @option{-mips3} option is used.
Assume that general purpose registers are 64 bits wide.
@item -mint64
@opindex mint64
......@@ -7072,31 +7090,32 @@ explanation of the default, and the width of pointers.
@opindex mlong32
Force long, int, and pointer types to be 32 bits wide.
If none of @option{-mlong32}, @option{-mlong64}, or @option{-mint64} are set,
the size of ints, longs, and pointers depends on the ABI and ISA chosen.
For @option{-mabi=32}, and @option{-mabi=n32}, ints and longs are 32 bits
wide. For @option{-mabi=64}, ints are 32 bits, and longs are 64 bits wide.
For @option{-mabi=eabi} and either @option{-mips1} or @option{-mips2}, ints
and longs are 32 bits wide. For @option{-mabi=eabi} and higher ISAs, ints
are 32 bits, and longs are 64 bits wide. The width of pointer types is
the smaller of the width of longs or the width of general purpose
registers (which in turn depends on the ISA)@.
The default size of ints, longs and pointers depends on the ABI@. All
the supported ABIs use 32-bit ints. The n64 ABI uses 64-bit longs, as
does the 64-bit Cygnus EABI; the others use 32-bit longs. Pointers
are the same size as longs, or the same size as integer registers,
whichever is smaller.
@item -mabi=32
@itemx -mabi=o64
@itemx -mabi=n32
@itemx -mabi=64
@itemx -mabi=eabi
@itemx -mabi=meabi
@opindex mabi=32
@opindex mabi=o64
@opindex mabi=n32
@opindex mabi=64
@opindex mabi=eabi
Generate code for the indicated ABI@. The default instruction level is
@option{-mips1} for @samp{32}, @option{-mips3} for @samp{n32}, and
@option{-mips4} otherwise. Conversely, with @option{-mips1} or
@option{-mips2}, the default ABI is @samp{32}; otherwise, the default ABI
is @samp{64}.
@opindex mabi=meabi
Generate code for the given ABI@.
Note that there are two embedded ABIs: @option{-mabi=eabi}
selects the one defined by Cygnus while @option{-meabi=meabi}
selects the one defined by MIPS@. Both these ABIs have
32-bit and 64-bit variants. Normally, GCC will generate
64-bit code when you select a 64-bit architecture, but you
can use @option{-mgp32} to get 32-bit code instead.
@item -mmips-as
@opindex mmips-as
......
gcc/testsuite/ChangeLog
2002-07-25 Richard Sandiford <rsandifo@redhat.com>
* gcc.dg/mips-args-[123].c: New tests.
2002-07-24 Aldy Hernandez <aldyh@redhat.com>
* gcc.dg/ppc-spe.c: New.
......
gcc/testsuite/gcc.dg/mips-args-1.c 0 → 100644
/* Check that certain preprocessor macros are defined, and do some
consistency checks. */
/* { dg-do compile { target mips*-*-* } } */
const char *compiled_for = _MIPS_ARCH;
const char *optimized_for = _MIPS_TUNE;
#if __mips_fpr != 32 && __mips_fpr != 64
#error Bad __mips_fpr
#endif
/* Test complementary macro pairs: exactly one of each pair
must be defined. */
#if defined (_R3000) == defined (_R4000)
#error _R3000 / _R4000 mismatch
#endif
#if defined (__mips_hard_float) == defined (__mips_soft_float)
#error __mips_hard_float / __mips_soft_float mismatch
#endif
#if defined (_MIPSEL) == defined (_MIPSEB)
#error _MIPSEL / _MIPSEB mismatch
#endif
/* Check for __mips64 consistency. */
#if defined (__mips64) != defined (_R4000)
#error __mips64 / _R4000 mismatch
#endif
#if defined (__mips64) && __mips != 3 && __mips != 4 && __mips != 64
#error __mips64 / __mips mismatch
#endif
gcc/testsuite/gcc.dg/mips-args-2.c 0 → 100644
/* Check the _MIPSEB and _MIPSEL macros are accurate. */
/* { dg-do run { target mips*-*-* } } */
short foo = 1;
int main ()
{
char *p = (char *) &foo;
#ifdef _MIPSEB
if (p[0] != 0 || p[1] != 1)
#else
if (p[0] != 1 || p[1] != 0)
#endif
abort ();
exit (0);
}
gcc/testsuite/gcc.dg/mips-args-3.c 0 → 100644
/* __mips, and related defines, guarantee that certain assembly
instructions can be used. Check a few examples. */
/* { dg-do run { target mips*-*-* } } */
typedef int int32 __attribute__ ((mode (SI)));
typedef int int64 __attribute__ ((mode (DI)));
int foo (float inf, int64 in64, int32 in32)
{
int64 res64;
int32 res32;
#if __mips != 1 && defined (__mips_hard_float)
__asm__ ("trunc.w.s %0, %1" : "=f" (res32) : "f" (inf));
if (res32 != 11)
abort ();
#endif
#if defined (__mips64)
__asm__ ("daddu %0, %1, %1" : "=r" (res64) : "r" (in64));
if (res64 != 50)
abort ();
#endif
#if (__mips == 4 || __mips == 32 || __mips == 64) && !defined (__mips16)
__asm__ ("move %0,%.\n\tmovn %0,%1,%2"
: "=&r" (res32) : "r" (in32), "r" (in64 != 0));
if (res32 != 60)
abort ();
#endif
}
int main ()
{
foo (11.4f, 25, 60);
exit (0);
}
gcc/toplev.c
......@@ -179,6 +179,11 @@ const char *dump_base_name;
extern int target_flags;
/* A mask of target_flags that includes bit X if X was set or cleared
on the command line. */
int target_flags_explicit;
/* Debug hooks - dependent upon command line options. */
const struct gcc_debug_hooks *debug_hooks = &do_nothing_debug_hooks;
......@@ -4411,6 +4416,13 @@ set_target_switch (name)
target_flags &= ~-target_switches[j].value;
else
target_flags |= target_switches[j].value;
if (name[0] != 0)
{
if (target_switches[j].value < 0)
target_flags_explicit |= -target_switches[j].value;
else
target_flags_explicit |= target_switches[j].value;
}
valid_target_option = 1;
}
......
gcc/toplev.h
......@@ -108,6 +108,7 @@ extern void check_global_declarations PARAMS ((union tree_node **, int));
extern const char *progname;
extern const char *dump_base_name;
extern int target_flags_explicit;
/* The hashtable, so that the C front ends can pass it to cpplib. */
extern struct ht *ident_hash;
......
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