Commit a2027aad by Segher Boessenkool Committed by Segher Boessenkool

predicates.md (altivec_register_operand, [...]): If op is a SUBREG, consider its…

predicates.md (altivec_register_operand, [...]): If op is a SUBREG, consider its SUBREG_REG instead.

gcc/
	* config/rs6000/predicates.md (altivec_register_operand,
	vsx_register_operand, vfloat_operand, vint_operand,
	vlogical_operand, gpc_reg_operand, cc_reg_operand,
	cc_reg_not_cr0_operand, cc_reg_not_micro_cr0_operand):
	If op is a SUBREG, consider its SUBREG_REG instead.

From-SVN: r191645
parent 699bae64
2012-09-22 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicates.md (altivec_register_operand,
vsx_register_operand, vfloat_operand, vint_operand,
vlogical_operand, gpc_reg_operand, cc_reg_operand,
cc_reg_not_cr0_operand, cc_reg_not_micro_cr0_operand):
If op is a SUBREG, consider its SUBREG_REG instead.
2012-09-22 Uros Bizjak <ubizjak@gmail.com> 2012-09-22 Uros Bizjak <ubizjak@gmail.com>
* optabs.c (prepare_cmp_insn): Expand comparison of the result * optabs.c (prepare_cmp_insn): Expand comparison of the result
......
...@@ -30,44 +30,89 @@ ...@@ -30,44 +30,89 @@
(and (match_code "reg") (and (match_code "reg")
(match_test "REGNO (op) == CTR_REGNO (match_test "REGNO (op) == CTR_REGNO
|| REGNO (op) > LAST_VIRTUAL_REGISTER"))) || REGNO (op) > LAST_VIRTUAL_REGISTER")))
;; Return 1 if op is an Altivec register. ;; Return 1 if op is an Altivec register.
(define_predicate "altivec_register_operand" (define_predicate "altivec_register_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG {
|| ALTIVEC_REGNO_P (REGNO (op)) if (GET_CODE (op) == SUBREG)
|| REGNO (op) > LAST_VIRTUAL_REGISTER"))) op = SUBREG_REG (op);
if (!REG_P (op))
return 0;
if (REGNO (op) > LAST_VIRTUAL_REGISTER)
return 1;
return ALTIVEC_REGNO_P (REGNO (op));
})
;; Return 1 if op is a VSX register. ;; Return 1 if op is a VSX register.
(define_predicate "vsx_register_operand" (define_predicate "vsx_register_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG {
|| VSX_REGNO_P (REGNO (op)) if (GET_CODE (op) == SUBREG)
|| REGNO (op) > LAST_VIRTUAL_REGISTER"))) op = SUBREG_REG (op);
if (!REG_P (op))
return 0;
if (REGNO (op) > LAST_VIRTUAL_REGISTER)
return 1;
return VSX_REGNO_P (REGNO (op));
})
;; Return 1 if op is a vector register that operates on floating point vectors ;; Return 1 if op is a vector register that operates on floating point vectors
;; (either altivec or VSX). ;; (either altivec or VSX).
(define_predicate "vfloat_operand" (define_predicate "vfloat_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG {
|| VFLOAT_REGNO_P (REGNO (op)) if (GET_CODE (op) == SUBREG)
|| REGNO (op) > LAST_VIRTUAL_REGISTER"))) op = SUBREG_REG (op);
if (!REG_P (op))
return 0;
if (REGNO (op) > LAST_VIRTUAL_REGISTER)
return 1;
return VFLOAT_REGNO_P (REGNO (op));
})
;; Return 1 if op is a vector register that operates on integer vectors ;; Return 1 if op is a vector register that operates on integer vectors
;; (only altivec, VSX doesn't support integer vectors) ;; (only altivec, VSX doesn't support integer vectors)
(define_predicate "vint_operand" (define_predicate "vint_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG {
|| VINT_REGNO_P (REGNO (op)) if (GET_CODE (op) == SUBREG)
|| REGNO (op) > LAST_VIRTUAL_REGISTER"))) op = SUBREG_REG (op);
if (!REG_P (op))
return 0;
if (REGNO (op) > LAST_VIRTUAL_REGISTER)
return 1;
return VINT_REGNO_P (REGNO (op));
})
;; Return 1 if op is a vector register to do logical operations on (and, or, ;; Return 1 if op is a vector register to do logical operations on (and, or,
;; xor, etc.) ;; xor, etc.)
(define_predicate "vlogical_operand" (define_predicate "vlogical_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG {
|| VLOGICAL_REGNO_P (REGNO (op)) if (GET_CODE (op) == SUBREG)
|| REGNO (op) > LAST_VIRTUAL_REGISTER"))) op = SUBREG_REG (op);
if (!REG_P (op))
return 0;
if (REGNO (op) > LAST_VIRTUAL_REGISTER)
return 1;
return VLOGICAL_REGNO_P (REGNO (op));
})
;; Return 1 if op is the carry register. ;; Return 1 if op is the carry register.
(define_predicate "ca_operand" (define_predicate "ca_operand"
...@@ -123,36 +168,73 @@ ...@@ -123,36 +168,73 @@
;; Return 1 if op is a register that is not special. ;; Return 1 if op is a register that is not special.
(define_predicate "gpc_reg_operand" (define_predicate "gpc_reg_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "(GET_CODE (op) != REG {
|| (REGNO (op) >= ARG_POINTER_REGNUM if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
&& !CA_REGNO_P (REGNO (op))) return 0;
|| INT_REGNO_P (REGNO (op))
|| FP_REGNO_P (REGNO (op))) if (GET_CODE (op) == SUBREG)
&& !((TARGET_E500_DOUBLE || TARGET_SPE) op = SUBREG_REG (op);
&& invalid_e500_subreg (op, mode))")))
if (!REG_P (op))
return 0;
if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
return 1;
return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
})
;; Return 1 if op is a register that is a condition register field. ;; Return 1 if op is a register that is a condition register field.
(define_predicate "cc_reg_operand" (define_predicate "cc_reg_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG {
|| REGNO (op) > LAST_VIRTUAL_REGISTER if (GET_CODE (op) == SUBREG)
|| CR_REGNO_P (REGNO (op))"))) op = SUBREG_REG (op);
if (!REG_P (op))
return 0;
if (REGNO (op) > LAST_VIRTUAL_REGISTER)
return 1;
return CR_REGNO_P (REGNO (op));
})
;; Return 1 if op is a register that is a condition register field not cr0. ;; Return 1 if op is a register that is a condition register field not cr0.
(define_predicate "cc_reg_not_cr0_operand" (define_predicate "cc_reg_not_cr0_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG {
|| REGNO (op) > LAST_VIRTUAL_REGISTER if (GET_CODE (op) == SUBREG)
|| CR_REGNO_NOT_CR0_P (REGNO (op))"))) op = SUBREG_REG (op);
if (!REG_P (op))
return 0;
if (REGNO (op) > LAST_VIRTUAL_REGISTER)
return 1;
return CR_REGNO_NOT_CR0_P (REGNO (op));
})
;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0. ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
(define_predicate "cc_reg_not_micro_cr0_operand" (define_predicate "cc_reg_not_micro_cr0_operand"
(and (match_operand 0 "register_operand") (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG {
|| REGNO (op) > LAST_VIRTUAL_REGISTER if (GET_CODE (op) == SUBREG)
|| (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op))) op = SUBREG_REG (op);
|| (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
if (!REG_P (op))
return 0;
if (REGNO (op) > LAST_VIRTUAL_REGISTER)
return 1;
if (rs6000_gen_cell_microcode)
return CR_REGNO_NOT_CR0_P (REGNO (op));
else
return CR_REGNO_P (REGNO (op));
})
;; Return 1 if op is a constant integer valid for D field ;; Return 1 if op is a constant integer valid for D field
;; or non-special register register. ;; or non-special register register.
......
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