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lvzhengyang
riscv-gcc-1
Commits
a1fa0e6c
Commit
a1fa0e6c
authored
Apr 11, 2012
by
Oleg Endo
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sh.h: Remove old secondary reload code.
* config/sh/sh.h: Remove old secondary reload code. From-SVN: r186328
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e6b8b8c7
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gcc/ChangeLog
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a1fa0e6c
2012-04-11 Oleg Endo <olegendo@gcc.gnu.org>
2012-04-11 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.h: Remove old secondary reload code.
2012-04-11 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.c (SCHED_REORDER): Merge macro into ...
* config/sh/sh.c (SCHED_REORDER): Merge macro into ...
(ready_reorder): ... this function.
(ready_reorder): ... this function.
...
...
gcc/config/sh/sh.h
View file @
a1fa0e6c
...
@@ -1216,80 +1216,6 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
...
@@ -1216,80 +1216,6 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
#define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
(((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
(((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
#if 0
#define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
((((REGCLASS_HAS_FP_REG (CLASS) \
&& (REG_P (X) \
&& (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
|| (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
&& TARGET_FMOVD)))) \
|| (REGCLASS_HAS_GENERAL_REG (CLASS) \
&& REG_P (X) \
&& FP_REGISTER_P (REGNO (X)))) \
&& ! TARGET_SHMEDIA \
&& ((MODE) == SFmode || (MODE) == SImode)) \
? FPUL_REGS \
: (((CLASS) == FPUL_REGS \
|| (REGCLASS_HAS_FP_REG (CLASS) \
&& ! TARGET_SHMEDIA && MODE == SImode)) \
&& (MEM_P (X) \
|| (REG_P (X) \
&& (REGNO (X) >= FIRST_PSEUDO_REGISTER \
|| REGNO (X) == T_REG \
|| system_reg_operand (X, VOIDmode))))) \
? GENERAL_REGS \
: (((CLASS) == TARGET_REGS \
|| (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
&& !satisfies_constraint_Csy (X) \
&& (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
? GENERAL_REGS \
: (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
&& REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
&& (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
? GENERAL_REGS \
: ((CLASS) != GENERAL_REGS && REG_P (X) \
&& TARGET_REGISTER_P (REGNO (X))) \
? GENERAL_REGS : (ELSE))
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
((REGCLASS_HAS_FP_REG (CLASS) \
&& ! TARGET_SHMEDIA \
&& immediate_operand ((X), (MODE)) \
&& ! ((fp_zero_operand (X) || fp_one_operand (X)) \
&& (MODE) == SFmode && fldi_ok ())) \
? R0_REGS \
: ((CLASS) == FPUL_REGS \
&& ((REG_P (X) \
&& (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
|| REGNO (X) == T_REG)) \
|| GET_CODE (X) == PLUS)) \
? GENERAL_REGS \
: (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
? (satisfies_constraint_I08 (X) \
? GENERAL_REGS \
: R0_REGS) \
: ((CLASS) == FPSCR_REGS \
&& ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|| (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
? GENERAL_REGS \
: (REGCLASS_HAS_FP_REG (CLASS) \
&& TARGET_SHMEDIA \
&& immediate_operand ((X), (MODE)) \
&& (X) != CONST0_RTX (GET_MODE (X)) \
&& GET_MODE (X) != V4SFmode) \
? GENERAL_REGS \
: (((MODE) == QImode || (MODE) == HImode) \
&& TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
? GENERAL_REGS \
: (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
&& (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
? TARGET_REGS \
: SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
#endif
/* Return the maximum number of consecutive registers
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
needed to represent mode MODE in a register of class CLASS.
...
...
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