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Commit a1c6e4b8 by Trevor Smigiel Committed by Trevor Smigiel
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spu-protos.h (spu_split_immediate): Renamed from spu_split_address. 

        * config/spu/spu-protos.h (spu_split_immediate): Renamed from
        spu_split_address.
        (cpat_const_p, gen_cpat_const): Add.
        * config/spu/spu.c (immediate_class): New enum.
        (cpat_info, classify_immediate): New.
        (print_operand): Use S, D, T instead of F, G, H.  Use
        classify_immediate.  Handle cpat cases.
        (spu_split_immediate):  Renamed from spu_split_address.  Split all
        immediates that can be split.
        (immediate_load_p): Use classify_immediate.
        (spu_legitimate_constant_p): Accept everything except some cases of
        CONST_VECTOR.
        (spu_expand_move): Use spu_split_immedate.
        (fsmbi_const_p): Use classify_immediate.
        (cpat_const_p): New.
        (gen_cpat_const: New.
        * config/spu/constraints.md (j,k,l): New constraints for cpat
        instructions.
        * config/spu/spu.md (unnamed splitter): Change address splitter to
        handle all immediates.
        (_mov<mode>, _movdi, _movti): Handle i, j, k constraints for cpat
        instructions.
        (cpat, _cpat, splitter): Generate a TImode constant for cpat patterns
        when possible.

From-SVN: r119682
parent 55eb837d
Showing with 106 additions and 36 deletions
gcc/ChangeLog
2006-12-08 Trevor Smigiel <trevor_smigiel@playstation.sony.com>
* config/spu/spu-protos.h (spu_split_immediate): Renamed from
spu_split_address.
(cpat_const_p, gen_cpat_const): Add.
* config/spu/spu.c (immediate_class): New enum.
(cpat_info, classify_immediate): New.
(print_operand): Use S, D, T instead of F, G, H. Use
classify_immediate. Handle cpat cases.
(spu_split_immediate): Renamed from spu_split_address. Split all
immediates that can be split.
(immediate_load_p): Use classify_immediate.
(spu_legitimate_constant_p): Accept everything except some cases of
CONST_VECTOR.
(spu_expand_move): Use spu_split_immedate.
(fsmbi_const_p): Use classify_immediate.
(cpat_const_p): New.
(gen_cpat_const: New.
* config/spu/constraints.md (j,k,l): New constraints for cpat
instructions.
* config/spu/spu.md (unnamed splitter): Change address splitter to
handle all immediates.
(_mov<mode>, _movdi, _movti): Handle i, j, k constraints for cpat
instructions.
(cpat, _cpat, splitter): Generate a TImode constant for cpat patterns
when possible.
2006-12-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR target/30039
......
gcc/config/spu/constraints.md
......@@ -18,7 +18,7 @@
;; GCC standard constraints: g, i, m, n, o, p, r, s, E-H, I-P, V, X
;; unused for SPU: E-H, L, Q, d, e, h, j-l, q, t-z
;; unused for SPU: E-H, L, Q, d, e, h, q, t-z
;; For most immediate constraints we have 3 variations to deal with the
;; fact const_int has no mode. One variation treats const_int as 32 bit,
......@@ -84,6 +84,22 @@
"An immediate which can be loaded with fsmbi."
(and (match_code "const_int,const_double,const_vector")
(match_test "fsmbi_const_p (op)")))
(define_constraint "j"
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 32 bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "cpat_const_p (op, SImode)")))
(define_constraint "k"
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 64 bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "cpat_const_p (op, DImode)")))
(define_constraint "l"
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions."
(and (match_code "const_double,const_vector")
(match_test "cpat_const_p (op, TImode)")))
;; Integer constraints
......
gcc/config/spu/spu-protos.h
......@@ -34,7 +34,7 @@ extern HOST_WIDE_INT const_double_to_hwint (rtx x);
extern rtx hwint_to_const_double (enum machine_mode mode, HOST_WIDE_INT v);
extern void print_operand_address (FILE * file, register rtx addr);
extern void print_operand (FILE * file, rtx x, int code);
extern void spu_split_address (rtx * ops);
extern int spu_split_immediate (rtx * ops);
extern int spu_saved_regs_size (void);
extern int direct_return (void);
extern void spu_expand_prologue (void);
......@@ -69,6 +69,8 @@ extern void spu_split_load (rtx * ops);
extern void spu_split_store (rtx * ops);
extern int spu_valid_move (rtx * ops);
extern int fsmbi_const_p (rtx x);
extern int cpat_const_p (rtx x, enum machine_mode mode);
extern rtx gen_cpat_const (rtx * ops);
extern void constant_to_array (enum machine_mode mode, rtx x,
unsigned char *arr);
extern rtx array_to_constant (enum machine_mode mode, unsigned char *arr);
......
gcc/config/spu/spu.md
......@@ -238,26 +238,19 @@
})
(define_split
[(set (match_operand:SI 0 "spu_reg_operand" "=r")
(match_operand:SI 1 "immediate_operand" "s"))]
"(flag_pic || TARGET_LARGE_MEM
|| (GET_CODE (operands[1]) == CONST
&& !legitimate_const (operands[1], 0)))
&& (reload_in_progress || reload_completed)
&& (GET_CODE (operands[1]) == CONST
|| GET_CODE (operands[1]) == SYMBOL_REF
|| GET_CODE (operands[1]) == LABEL_REF)"
[(parallel
[(set (match_dup:SI 0)
(match_dup:SI 1))
(use (const_int 0))])
(set (match_dup:SI 0)
(plus:SI (match_dup:SI 0)
(match_dup:SI 2)))]
[(set (match_operand 0 "spu_reg_operand")
(match_operand 1 "immediate_operand"))]
""
[(set (match_dup 0)
(high (match_dup 1)))
(set (match_dup 0)
(lo_sum (match_dup 0)
(match_dup 1)))]
{
spu_split_address(operands);
DONE;
if (spu_split_immediate (operands))
DONE;
FAIL;
})
(define_insn "pic"
......@@ -285,16 +278,17 @@
;; move internal
(define_insn "_mov<mode>"
[(set (match_operand:MOV 0 "spu_nonimm_operand" "=r,r,r,r,m")
(match_operand:MOV 1 "spu_mov_operand" "r,A,f,m,r"))]
[(set (match_operand:MOV 0 "spu_nonimm_operand" "=r,r,r,r,r,m")
(match_operand:MOV 1 "spu_mov_operand" "r,A,f,j,m,r"))]
"spu_valid_move (operands)"
"@
ori\t%0,%1,0
il%s1\t%0,%S1
fsmbi\t%0,%F1
fsmbi\t%0,%S1
c%s1d\t%0,%S1($sp)
lq%p1\t%0,%1
stq%p0\t%1,%0"
[(set_attr "type" "fx2,fx2,shuf,load,store")])
[(set_attr "type" "fx2,fx2,shuf,shuf,load,store")])
(define_insn "high"
[(set (match_operand:SI 0 "spu_reg_operand" "=r")
......@@ -310,28 +304,30 @@
"iohl\t%0,%2@l")
(define_insn "_movdi"
[(set (match_operand:DI 0 "spu_nonimm_operand" "=r,r,r,r,m")
(match_operand:DI 1 "spu_mov_operand" "r,a,f,m,r"))]
[(set (match_operand:DI 0 "spu_nonimm_operand" "=r,r,r,r,r,m")
(match_operand:DI 1 "spu_mov_operand" "r,a,f,k,m,r"))]
"spu_valid_move (operands)"
"@
ori\t%0,%1,0
il%d1\t%0,%D1
fsmbi\t%0,%G1
fsmbi\t%0,%D1
c%d1d\t%0,%D1($sp)
lq%p1\t%0,%1
stq%p0\t%1,%0"
[(set_attr "type" "fx2,fx2,shuf,load,store")])
[(set_attr "type" "fx2,fx2,shuf,shuf,load,store")])
(define_insn "_movti"
[(set (match_operand:TI 0 "spu_nonimm_operand" "=r,r,r,r,m")
(match_operand:TI 1 "spu_mov_operand" "r,U,f,m,r"))]
[(set (match_operand:TI 0 "spu_nonimm_operand" "=r,r,r,r,r,m")
(match_operand:TI 1 "spu_mov_operand" "r,U,f,l,m,r"))]
"spu_valid_move (operands)"
"@
ori\t%0,%1,0
il%t1\t%0,%T1
fsmbi\t%0,%H1
fsmbi\t%0,%T1
c%t1d\t%0,%T1($sp)
lq%p1\t%0,%1
stq%p0\t%1,%0"
[(set_attr "type" "fx2,fx2,shuf,load,store")])
[(set_attr "type" "fx2,fx2,shuf,shuf,load,store")])
(define_insn_and_split "load"
[(set (match_operand 0 "spu_reg_operand" "=r")
......@@ -358,10 +354,26 @@
{ spu_split_store(operands); DONE; })
;; Operand 3 is the number of bytes. 1:b 2:h 4:w 8:d
(define_insn "cpat"
(define_expand "cpat"
[(set (match_operand:TI 0 "spu_reg_operand" "=r,r")
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "r,r")
(match_operand:SI 2 "spu_nonmem_operand" "r,n")
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "r,r")
(match_operand:SI 2 "spu_nonmem_operand" "r,n")
(match_operand:SI 3 "immediate_operand" "i,i")] UNSPEC_CPAT))]
""
{
rtx x = gen_cpat_const (operands);
if (x)
{
emit_move_insn (operands[0], x);
DONE;
}
})
(define_insn "_cpat"
[(set (match_operand:TI 0 "spu_reg_operand" "=r,r")
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "r,r")
(match_operand:SI 2 "spu_nonmem_operand" "r,n")
(match_operand:SI 3 "immediate_operand" "i,i")] UNSPEC_CPAT))]
""
"@
......@@ -369,6 +381,19 @@
c%M3d\t%0,%C2(%1)"
[(set_attr "type" "shuf")])
(define_split
[(set (match_operand:TI 0 "spu_reg_operand")
(unspec:TI [(match_operand:SI 1 "spu_nonmem_operand")
(match_operand:SI 2 "immediate_operand")
(match_operand:SI 3 "immediate_operand")] UNSPEC_CPAT))]
""
[(set (match_dup:TI 0)
(match_dup:TI 4))]
{
operands[4] = gen_cpat_const (operands);
if (!operands[4])
FAIL;
})
;; extend
......
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