Handle misaligned TFmode load/store.

gcc/

2011-05-30  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/49168
	* config/i386/i386.md (*movtf_internal): Handle misaligned
	load/store.

gcc/testsuite/

2011-05-30  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/49168
	 * gcc.target/i386/pr49168-1.c: New.

From-SVN: r174451

gcc/ChangeLog

+2011-05-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/49168
+	* config/i386/i386.md (*movtf_internal): Handle misaligned
+	load/store.
+
 2011-05-30  Jakub Jelinek  <jakub@redhat.com>
 
 	* dwarf2out.c (modified_type_die, gen_reference_type_die): Use

gcc/config/i386/i386.md

@@ -2842,10 +2842,23 @@
     {
     case 0:
     case 1:
-      if (get_attr_mode (insn) == MODE_V4SF)
-	return "%vmovaps\t{%1, %0|%0, %1}";
+      /* Handle misaligned load/store since we don't have movmisaligntf
+	 pattern. */
+      if (misaligned_operand (operands[0], TFmode)
+	  || misaligned_operand (operands[1], TFmode))
+	{
+	  if (get_attr_mode (insn) == MODE_V4SF)
+	    return "%vmovups\t{%1, %0|%0, %1}";
+	  else
+	    return "%vmovdqu\t{%1, %0|%0, %1}";
+	}
       else
-	return "%vmovdqa\t{%1, %0|%0, %1}";
+	{
+	  if (get_attr_mode (insn) == MODE_V4SF)
+	    return "%vmovaps\t{%1, %0|%0, %1}";
+	  else
+	    return "%vmovdqa\t{%1, %0|%0, %1}";
+	}
 
     case 2:
       return standard_sse_constant_opcode (insn, operands[1]);

gcc/testsuite/ChangeLog

+2011-05-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/49168
+	 * gcc.target/i386/pr49168-1.c: New.
+
 2011-05-30  Jakub Jelinek  <jakub@redhat.com>
 	    Eric Botcazou  <ebotcazou@adacore.com>
 

gcc/testsuite/gcc.target/i386/pr49168-1.c

+/* PR target/49168  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movdqa\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+/* { dg-final { scan-assembler "movdqu\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+
+void
+flt128_va (void *mem, __float128 d)
+{ 
+  __builtin_memcpy (mem, &d, sizeof (d));
+}