Skip to content

R
riscv-gcc-1
Commit a0a31d1e by Bernd Schmidt Committed by Bernd Schmidt
Options

bfin.md (sp_or_sm, [...]): New macro. 

gcc/
	* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
	(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
	ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
	ssaddhi3_parts and sssubhi3_parts.
	(flag_mulhi3_parts): Produce a HImode output rather than trying to set
	a VEC_SELECT.
	* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
	Adjust accordingly.

gcc/testsuite/
	* gcc.target/bfin/20090411-1.c: New test.

From-SVN: r146929
parent 5f3153cd
Showing with 117 additions and 73 deletions
gcc/ChangeLog
2009-04-29 Bernd Schmidt <bernd.schmidt@analog.com>
* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
ssaddhi3_parts and sssubhi3_parts.
(flag_mulhi3_parts): Produce a HImode output rather than trying to set
a VEC_SELECT.
* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
Adjust accordingly.
2009-04-28 Richard Guenther <rguenther@suse.de>
* tree-vect-loop.c (get_initial_def_for_induction): Use
......
gcc/config/bfin/bfin.c
......@@ -6169,15 +6169,14 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
emit_insn (gen_flag_mulv2hi (tmp1, op0, op0, GEN_INT (MACFLAG_NONE)));
emit_insn (gen_flag_mulhi_parts (tmp2, op0, op0, const0_rtx,
emit_insn (gen_flag_mulhi_parts (gen_lowpart (HImode, tmp2), op0, op0,
const0_rtx, const1_rtx,
GEN_INT (MACFLAG_NONE)));
emit_insn (gen_ssaddhi3_parts (target, tmp2, tmp2, const1_rtx,
const0_rtx, const0_rtx));
emit_insn (gen_sssubhi3_parts (target, tmp1, tmp1, const0_rtx,
const0_rtx, const1_rtx));
emit_insn (gen_ssaddhi3_high_parts (target, tmp2, tmp2, tmp2, const0_rtx,
const0_rtx));
emit_insn (gen_sssubhi3_low_parts (target, target, tmp1, tmp1,
const0_rtx, const1_rtx));
return target;
......
gcc/config/bfin/bfin.md
......@@ -2962,74 +2962,82 @@
;; Unusual arithmetic operations on 16-bit registers.
(define_insn "ssaddhi3"
(define_code_iterator sp_or_sm [ss_plus ss_minus])
(define_code_attr spm_string [(ss_plus "+") (ss_minus "-")])
(define_code_attr spm_name [(ss_plus "add") (ss_minus "sub")])
(define_insn "ss<spm_name>hi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(ss_plus:HI (match_operand:HI 1 "register_operand" "d")
(sp_or_sm:HI (match_operand:HI 1 "register_operand" "d")
(match_operand:HI 2 "register_operand" "d")))]
""
"%h0 = %h1 + %h2 (S)%!"
"%h0 = %h1 <spm_string> %h2 (S)%!"
[(set_attr "type" "dsp32")])
(define_insn "ssaddhi3_parts"
[(set (vec_select:HI
(match_operand:V2HI 0 "register_operand" "d")
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
(ss_plus:HI (vec_select:HI
(match_operand:V2HI 1 "register_operand" "d")
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
(vec_select:HI
(match_operand:V2HI 2 "register_operand" "d")
(parallel [(match_operand 5 "const01_operand" "P0P1")]))))]
""
(define_insn "ss<spm_name>hi3_parts"
[(set (match_operand:HI 0 "register_operand" "=d")
(sp_or_sm:HI (vec_select:HI
(match_operand:V2HI 1 "register_operand" "d")
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
(vec_select:HI
(match_operand:V2HI 2 "register_operand" "d")
(parallel [(match_operand 4 "const01_operand" "P0P1")]))))]
""
{
const char *templates[] = {
"%h0 = %h1 + %h2 (S)%!",
"%d0 = %h1 + %h2 (S)%!",
"%h0 = %d1 + %h2 (S)%!",
"%d0 = %d1 + %h2 (S)%!",
"%h0 = %h1 + %d2 (S)%!",
"%d0 = %h1 + %d2 (S)%!",
"%h0 = %d1 + %d2 (S)%!",
"%d0 = %d1 + %d2 (S)%!" };
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
+ (INTVAL (operands[5]) << 2);
"%h0 = %h1 <spm_string> %h2 (S)%!",
"%h0 = %d1 <spm_string> %h2 (S)%!",
"%h0 = %h1 <spm_string> %d2 (S)%!",
"%h0 = %d1 <spm_string> %d2 (S)%!" };
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
return templates[alt];
}
[(set_attr "type" "dsp32")])
(define_insn "sssubhi3_parts"
[(set (vec_select:HI
(match_operand:V2HI 0 "register_operand" "d")
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
(ss_minus:HI (vec_select:HI
(match_operand:V2HI 1 "register_operand" "d")
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
(vec_select:HI
(match_operand:V2HI 2 "register_operand" "d")
(parallel [(match_operand 5 "const01_operand" "P0P1")]))))]
""
(define_insn "ss<spm_name>hi3_low_parts"
[(set (match_operand:V2HI 0 "register_operand" "=d")
(vec_concat:V2HI
(vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
(parallel [(const_int 0)]))
(sp_or_sm:HI (vec_select:HI
(match_operand:V2HI 2 "register_operand" "d")
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
(vec_select:HI
(match_operand:V2HI 3 "register_operand" "d")
(parallel [(match_operand 5 "const01_operand" "P0P1")])))))]
""
{
const char *templates[] = {
"%h0 = %h1 - %h2 (S)%!",
"%d0 = %h1 - %h2 (S)%!",
"%h0 = %d1 - %h2 (S)%!",
"%d0 = %d1 - %h2 (S)%!",
"%h0 = %h1 - %d2 (S)%!",
"%d0 = %h1 - %d2 (S)%!",
"%h0 = %d1 - %d2 (S)%!",
"%d0 = %d1 - %d2 (S)%!" };
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
+ (INTVAL (operands[5]) << 2);
"%h0 = %h2 <spm_string> %h3 (S)%!",
"%h0 = %d2 <spm_string> %h3 (S)%!",
"%h0 = %h2 <spm_string> %d3 (S)%!",
"%h0 = %d2 <spm_string> %d3 (S)%!" };
int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
return templates[alt];
}
[(set_attr "type" "dsp32")])
(define_insn "sssubhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(ss_minus:HI (match_operand:HI 1 "register_operand" "d")
(match_operand:HI 2 "register_operand" "d")))]
""
"%h0 = %h1 - %h2 (S)%!"
(define_insn "ss<spm_name>hi3_high_parts"
[(set (match_operand:V2HI 0 "register_operand" "=d")
(vec_concat:V2HI
(sp_or_sm:HI (vec_select:HI
(match_operand:V2HI 2 "register_operand" "d")
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
(vec_select:HI
(match_operand:V2HI 3 "register_operand" "d")
(parallel [(match_operand 5 "const01_operand" "P0P1")])))
(vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
(parallel [(const_int 1)]))))]
""
{
const char *templates[] = {
"%d0 = %h2 <spm_string> %h3 (S)%!",
"%d0 = %d2 <spm_string> %h3 (S)%!",
"%d0 = %h2 <spm_string> %d3 (S)%!",
"%d0 = %d2 <spm_string> %d3 (S)%!" };
int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
return templates[alt];
}
[(set_attr "type" "dsp32")])
;; V2HI vector insns
......@@ -3239,30 +3247,23 @@
[(set_attr "type" "dsp32")])
(define_insn "flag_mulhi_parts"
[(set (vec_select:HI
(match_operand:V2HI 0 "register_operand" "d")
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
[(set (match_operand:HI 0 "register_operand" "=d")
(unspec:HI [(vec_select:HI
(match_operand:V2HI 1 "register_operand" "d")
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
(vec_select:HI
(match_operand:V2HI 2 "register_operand" "d")
(parallel [(match_operand 5 "const01_operand" "P0P1")]))
(match_operand 6 "const_int_operand" "n")]
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
(match_operand 5 "const_int_operand" "n")]
UNSPEC_MUL_WITH_FLAG))]
""
{
const char *templates[] = {
"%h0 = %h1 * %h2 %M6%!",
"%d0 = %h1 * %h2 %M6%!",
"%h0 = %d1 * %h2 %M6%!",
"%d0 = %d1 * %h2 %M6%!",
"%h0 = %h1 * %d2 %M6%!",
"%d0 = %h1 * %d2 %M6%!",
"%h0 = %d1 * %d2 %M6%!",
"%d0 = %d1 * %d2 %M6%!" };
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
+ (INTVAL (operands[5]) << 2);
"%h0 = %h1 * %h2 %M5%!",
"%h0 = %d1 * %h2 %M5%!",
"%h0 = %h1 * %d2 %M5%!",
"%h0 = %d1 * %d2 %M5%!" };
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
return templates[alt];
}
[(set_attr "type" "dsp32")])
......
gcc/testsuite/ChangeLog
2009-04-29 Bernd Schmidt <bernd.schmidt@analog.com>
* gcc.target/bfin/20090411-1.c: New test.
2009-04-29 Anmol P. Paralkar <anmol@freescale.com>
PR target/39565
......
gcc/testsuite/gcc.target/bfin/20090411-1.c 0 → 100644
/* { dg-do compile { target bfin-*-* } } */
/* { dg-options "-O2" } */
typedef short __v2hi __attribute__ ((vector_size (4)));
typedef __v2hi raw2x16;
typedef raw2x16 fract2x16;
typedef short fract16;
typedef struct complex_fract16
{
fract16 re;
fract16 im;
} __attribute__ ((aligned (4))) complex_fract16;
__inline__ __attribute__ ((always_inline))
static complex_fract16 csqu_fr16 (complex_fract16 _a)
{
complex_fract16 _x;
fract2x16 i =
__builtin_bfin_csqu_fr16 (__builtin_bfin_compose_2x16 ((_a).im, (_a).re));
(_x).re = __builtin_bfin_extract_lo (i);
(_x).im = __builtin_bfin_extract_hi (i);
return _x;
}
complex_fract16 f (complex_fract16 _a)
{
return csqu_fr16 (_a);
}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment