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riscv-gcc-1
Commit a0a301fc by Doug Evans
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sparc.h (SPARC_V9,SPARC_ARCH64): Delete. 

	* sparc/sparc.h (SPARC_V9,SPARC_ARCH64): Delete.
	(DEFAULT_ARCH32_P): New macro.
	(TARGET_ARCH{32,64}): Allow compile time or runtime selection.
	(enum cmodel): Declare.
	(sparc_cmodel_string,sparc_cmodel): Declare.
	(SPARC_DEFAULT_CMODEL): Provide default.
	(TARGET_{MEDLOW,MEDANY}): Renamed to TARGET_CM_{MEDLOW,MEDANY}.
	(TARGET_FULLANY): Deleted.
	(TARGET_CM_MEDMID): New macro.
	(CPP_CPU_DEFAULT_SPEC): Renamed from CPP_DEFAULT_SPEC.
	(ASM_CPU_DEFAULT_SPEC): Renamed from ASM_DEFAULT_SPEC.
	(CPP_PREDEFINES): Take out stuff now handled by %(cpp_arch).
	(CPP_SPEC): Rewrite.
	(CPP_ARCH{,32,64,_DEFAULT}_SPEC): New macros.
	(CPP_{ENDIAN,SUBTARGET}_SPEC): New macros.
	(ASM_ARCH{,32,64,_DEFAULT}_SPEC): New macros.
	(ASM_SPEC): Add %(asm_arch).
	(EXTRA_SPECS): Rename cpp_default to cpp_cpu_default.
	Rename asm_default to asm_cpu_default.
	Add cpp_arch32, cpp_arch64, cpp_arch_default, cpp_arch, cpp_endian,
	cpp_subtarget, asm_arch32, asm_arch64, asm_arch_default, asm_arch.
	(NO_BUILTIN_{PTRDIFF,SIZE}_TYPE): Define ifdef SPARC_BI_ARCH.
	({PTRDIFF,SIZE}_TYPE): Provide 32 and 64 bit values.
	(MASK_INT64,MASK_LONG64): Delete.
	(MASK_ARCH64): Renamed to MASK_64BIT.
	(MASK_{MEDLOW,MEDANY,FULLANY,CODE_MODEL}): Delete.
	(EMBMEDANY_BASE_REG): Renamed from MEDANY_BASE_REG.
	(TARGET_SWITCHES): Always provide 64 bit options.
	(ARCH64_SWITCHES): Delete.
	(TARGET_OPTIONS): New option -mcmodel=.
	(INT_TYPE_SIZE): Always 32.
	(MAX_LONG_TYPE_SIZE): Define ifdef SPARC_BI_ARCH.
	(INIT_EXPANDERS): sparc64_init_expanders renamed to sparc_init_....
	(FUNCTION_{,BLOCK_}PROFILER): Delete TARGET_EMBMEDANY support.
	(PRINT_OPERAND_PUNCT_VALID_P): Add '_'.
	* sparc/linux-aout.h (CPP_PREDEFINES): Take out stuff handled by
	CPP_SPEC.
	(CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC.
	* sparc/linux.h: Likewise.
	* sparc/linux64.h (SPARC_V9,SPARC_ARCH64): Delete.
	(ASM_CPU_DEFAULT_SPEC): Renamed from ASM_DEFAULT_SPEC.
	(TARGET_DEFAULT): Delete MASK_LONG64, MASK_MEDANY, add MASK_64BIT.
	(SPARC_DEFAULT_CMODEL): Define.
	(CPP_PREDEFINES): Take out stuff handled by CPP_SPEC.
	(CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC.
	(LONG_DOUBLE_TYPE_SIZE): Define.
	(ASM_SPEC): Add %(asm_arch).
	* sparc/sol2.h (CPP_PREDEFINES): Take out stuff handled by CPP_SPEC.
	(CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC.
	(TARGET_CPU_DEFAULT): Add ultrasparc case.
	* sparc/sp64-aout.h (SPARC_V9,SPARC_ARCH64): Delete.
	(TARGET_DEFAULT): MASK_ARCH64 renamed to MASK_64BIT.
	(SPARC_DEFAULT_CMODEL): Define.
	* sparc/sp64-elf.h (SPARC_V9,SPARC_ARCH64): Delete.
	(TARGET_DEFAULT): MASK_ARCH64 renamed to MASK_64BIT.  Delete
	MASK_LONG64, MASK_MEDANY.
	(SPARC_DEFAULT_CMODEL): Define.
	(CPP_PREDEFINES): Delete.
	(CPP_SUBTARGET_SPEC): Renamed from CPP_SPEC.
	(ASM_SPEC): Add %(asm_arch).
	(LONG_DOUBLE_TYPE_SIZE): Define.
	(DWARF2_DEBUGGING_INFO): Define.
	* sparc/splet.h (CPP_SPEC): Delete.
	* sparc/sysv4.h (CPP_PREDEFINES): Take out stuff handled by CPP_SPEC.
	(FUNCTION_BLOCK_PROFILER): Delete TARGET_EMBMEDANY support.
	(BLOCK_PROFILER): Likewise.
	* sparc/sparc.c (sparc_cmodel_string,sparc_cmodel): New globals.
	(sparc_override_options): Handle code model selection.
	(sparc_init_expanders): Renamed from sparc64_init_expanders.
	* sparc/sparc.md: TARGET_<code_model> renamed to TARGET_CM_....
	TARGET_MEDANY renamed to TARGET_CM_EMBMEDANY.
	(sethi_di_embmedany_{data,text}): Renamed from sethi_di_medany_....
	(sethi_di_fullany): Delete.

From-SVN: r16108
parent 2d5b6dea
Showing with 155 additions and 143 deletions
gcc/config/sparc/linux-aout.h
......@@ -70,10 +70,11 @@ Boston, MA 02111-1307, USA. */
#define WCHAR_TYPE_SIZE BITS_PER_WORD
#undef CPP_PREDEFINES
#define CPP_PREDEFINES "-Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)"
#define CPP_PREDEFINES "-Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)"
#undef CPP_SPEC
#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE}"
#undef CPP_SUBTARGET_SPEC
#define CPP_SUBTARGET_SPEC \
"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
/* Don't default to pcc-struct-return, because gcc is the only compiler,
and we want to retain compatibility with older gcc versions. */
......
gcc/config/sparc/linux.h
......@@ -42,6 +42,7 @@ Boston, MA 02111-1307, USA. */
/* Use stabs instead of DWARF debug format. */
#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
#include <sparc/sysv4.h>
#undef MD_EXEC_PREFIX
......@@ -102,13 +103,15 @@ Boston, MA 02111-1307, USA. */
#define WCHAR_TYPE_SIZE BITS_PER_WORD
#undef CPP_PREDEFINES
#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)"
#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)"
#undef CPP_SPEC
#undef CPP_SUBTARGET_SPEC
#ifdef USE_GNULIBC_1
#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE}"
#define CPP_SUBTARGET_SPEC \
"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
#else
#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__} %{msupersparc:-D__supersparc__ -D__sparc_v8__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
#define CPP_SUBTARGET_SPEC \
"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
#endif
#undef LIB_SPEC
......
gcc/config/sparc/linux64.h
......@@ -19,13 +19,11 @@ along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#define LINUX_DEFAULT_ELF
/* This is a v9 only compiler. -mv8 is not expected to work. If you want
a v8/v9 compiler, this isn't the place to do it. */
/* ??? bi-architecture support will require changes to the linker
related specs, among perhaps other things (multilibs). */
/* #define SPARC_BI_ARCH */
#define SPARC_V9 1 /* See sparc.h. */
#define SPARC_ARCH64 1
#define LINUX_DEFAULT_ELF
/* Don't assume anything about the header files. */
#define NO_IMPLICIT_EXTERN_C
......@@ -47,8 +45,8 @@ Boston, MA 02111-1307, USA. */
fprintf (FILE, "\t.version\t\"01.01\"\n"); \
} while (0)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-Av9a"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC "-Av9a"
#undef LIBGCC_SPEC
#define LIBGCC_SPEC \
......@@ -78,13 +76,17 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (sparc64 Linux/ELF)");
/* A v9 compiler with stack-bias, 32 bit integers, 64 bit longs and
64 bit pointers, in a Medium/Anywhere code model environment. */
/* A 64 bit v9 compiler with stack-bias,
in a Medium/Anywhere code model environment. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_ARCH64 + MASK_LONG64 + MASK_PTR64 /* + MASK_HARD_QUAD */ \
+ MASK_STACK_BIAS + MASK_MEDANY + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
/* The default code model. */
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_MEDANY
#undef SIZE_TYPE
#define SIZE_TYPE "long long unsigned int"
......@@ -97,20 +99,17 @@ Boston, MA 02111-1307, USA. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE BITS_PER_WORD
#undef LONG_DOUBLE_TYPE_SIZE
#define LONG_DOUBLE_TYPE_SIZE 128
#undef CPP_PREDEFINES
#define CPP_PREDEFINES "-D__sparc__ -D__sparc__ -D__sparc_v9__ -D__arch64__ -D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(sparc) -Amachine(sparc)"
#define CPP_PREDEFINES "-D__ELF__ -Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)"
#undef CPP_SPEC
#define CPP_SPEC "\
#undef CPP_SUBTARGET_SPEC
#define CPP_SUBTARGET_SPEC "\
%{fPIC:-D__PIC__ -D__pic__} \
%{fpic:-D__PIC__ -D__pic__} \
%{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
%{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
%{mlittle-endian:-D__LITTLE_ENDIAN__} \
%{msparclite:-D__sparclite__} \
%{mv8:-D__sparc_v8__} \
%{msupersparc:-D__supersparc__ -D__sparc_v8__} \
%{posix:-D_POSIX_SOURCE} \
"
/* We no longer link with libc_p.a or libg.a by default. If you
......@@ -162,7 +161,7 @@ Boston, MA 02111-1307, USA. */
%{Wa,*:%*} \
-s %{fpic:-K PIC} %{fPIC:-K PIC} \
%{mlittle-endian:-EL} \
%(asm_cpu) \
%(asm_cpu) %(asm_arch) \
"
/* Same as sparc.h */
......
gcc/config/sparc/sol2.h
......@@ -25,14 +25,12 @@ Boston, MA 02111-1307, USA. */
#undef CPP_PREDEFINES
#define CPP_PREDEFINES \
"-Dsun -Dsparc -Dunix -D__svr4__ -D__SVR4 \
-Asystem(unix) -Asystem(svr4) -Acpu(sparc) -Amachine(sparc)\
-D__GCC_NEW_VARARGS__"
"-Dsparc -Dsun -Dunix -D__svr4__ -D__SVR4 \
-Asystem(unix) -Asystem(svr4)"
#undef CPP_SPEC
#define CPP_SPEC "\
#undef CPP_SUBTARGET_SPEC
#define CPP_SUBTARGET_SPEC "\
%{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude} \
%(cpp_cpu) \
"
/* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
......@@ -46,15 +44,19 @@ Boston, MA 02111-1307, USA. */
/* This is here rather than in sparc.h because it's not known what
other assemblers will accept. */
#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-xarch=v8plus"
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plus"
#endif
#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusa"
#endif
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC "\
%{mcpu=v8plus:-xarch=v8plus} \
%{mcpu=ultrasparc:-xarch=v8plus} \
%{!mcpu*:%(asm_default)} \
%{mcpu=ultrasparc:-xarch=v8plusa} \
%{!mcpu*:%(asm_cpu_default)} \
"
/* However it appears that Solaris 2.0 uses the same reg numbering as
......
gcc/config/sparc/sp64-aout.h
/* Definitions of target machine for GNU compiler, for SPARC64, a.out.
Copyright (C) 1994, 1996 Free Software Foundation, Inc.
Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc.
Contributed by Doug Evans, dje@cygnus.com.
This file is part of GNU CC.
......@@ -19,14 +19,6 @@ along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* This is a v9 only compiler. -mv8 is not expected to work. If you want
a v8/v9 compiler, this isn't the place to do it.
The only code model supported is Medium/Low. */
#define SPARC_V9 1 /* See sparc.h. */
#define SPARC_ARCH64 1
#include "sparc/sparc.h"
#include "aoutos.h"
......@@ -35,5 +27,9 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_ARCH64 + MASK_PTR64 + MASK_HARD_QUAD \
+ MASK_MEDLOW + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
+ MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
/* The only code model supported is Medium/Low. */
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_MEDLOW
gcc/config/sparc/sp64-elf.h
......@@ -19,12 +19,6 @@ along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* This is a v9 only compiler. -mcpu=v8 is not expected to work. If you want
a v8/v9 compiler, this isn't the place to do it. */
#define SPARC_V9 1 /* See sparc.h. */
#define SPARC_ARCH64 1
/* ??? We're taking the scheme of including another file and then overriding
the values we don't like a bit too far here. The alternative is to more or
less duplicate all of svr4.h, sparc/sysv4.h, and sparc/sol2.h here
......@@ -35,30 +29,22 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (sparc64-elf)")
/* A v9 compiler without stack-bias, lp64 sizes,
/* A 64 bit v9 compiler without stack-bias,
in a Medium/Anywhere code model environment.
There is no stack bias as this configuration is intended for
embedded systems. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_ARCH64 + MASK_PTR64 + MASK_LONG64 + MASK_HARD_QUAD \
MASK_MEDANY + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
/* __svr4__ is used by the C library */
/* ??? __arch64__ is subject to change. */
#undef CPP_PREDEFINES
#define CPP_PREDEFINES "\
-D__sparc__ -D__sparc_v9__ -D__arch64__ -D__svr4__ \
-Acpu(sparc64) -Amachine(sparc64) \
"
(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
+ MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
#undef CPP_SPEC
#define CPP_SPEC "\
%{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
%{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
%{mlittle-endian:-D__LITTLE_ENDIAN__} \
"
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
/* __svr4__ is used by the C library (FIXME) */
#undef CPP_SUBTARGET_SPEC
#define CPP_SUBTARGET_SPEC "-D__svr4__"
#undef MD_EXEC_PREFIX
#undef MD_STARTFILE_PREFIX
......@@ -67,6 +53,7 @@ Boston, MA 02111-1307, USA. */
#define ASM_SPEC "\
%{v:-V} -s %{fpic:-K PIC} %{fPIC:-K PIC} \
%{mlittle-endian:-EL} \
%(asm_cpu) %(asm_arch) \
"
/* This is taken from sol2.h. */
......@@ -102,16 +89,6 @@ crtbegin.o%s \
#undef WORDS_BIG_ENDIAN
#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
/* Unfortunately, svr4.h redefines these so we have to restore them to
their original values in sparc.h. */
/* ??? It might be possible to eventually get svr4.h to do the right thing. */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long long int"
#undef SIZE_TYPE
#define SIZE_TYPE "long long unsigned int"
/* ??? This should be 32 bits for v9 but what can we do? */
#undef WCHAR_TYPE
#define WCHAR_TYPE "short unsigned int"
......@@ -119,6 +96,14 @@ crtbegin.o%s \
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 16
#undef LONG_DOUBLE_TYPE_SIZE
#define LONG_DOUBLE_TYPE_SIZE 128
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long long int"
#undef SIZE_TYPE
#define SIZE_TYPE "long long unsigned int"
/* The medium/anywhere code model practically requires us to put jump tables
in the text section as gcc is unable to distinguish LABEL_REF's of jump
tables from other label refs (when we need to). */
......@@ -131,6 +116,7 @@ crtbegin.o%s \
anyway so it is the default. */
#define DWARF_DEBUGGING_INFO
#define DWARF2_DEBUGGING_INFO
#define DBX_DEBUGGING_INFO
#undef PREFERRED_DEBUGGING_TYPE
......
gcc/config/sparc/sparc.c
......@@ -105,7 +105,12 @@ static void sparc_init_modes ();
/* Option handling. */
/* Record options as passed by user. */
/* Code model option as passed by user. */
char *sparc_cmodel_string;
/* Parsed value. */
enum cmodel sparc_cmodel;
/* Record alignment options as passed by user. */
char *sparc_align_loops_string;
char *sparc_align_jumps_string;
char *sparc_align_funcs_string;
......@@ -133,16 +138,30 @@ enum processor_type sparc_cpu;
void
sparc_override_options ()
{
static struct code_model {
char *name;
int value;
} cmodels[] = {
{ "32", CM_32 },
{ "medlow", CM_MEDLOW },
{ "medmid", CM_MEDMID },
{ "medany", CM_MEDANY },
{ "embmedany", CM_EMBMEDANY },
{ 0, 0 }
};
struct code_model *cmodel;
/* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
static struct cpu_default {
int cpu;
char *name;
} cpu_default[] = {
/* There must be one entry here for each TARGET_CPU value. */
{ TARGET_CPU_sparc, "cypress" },
{ TARGET_CPU_v8, "v8" },
{ TARGET_CPU_supersparc, "supersparc" },
{ TARGET_CPU_sparclet, "tsc701" },
{ TARGET_CPU_sparclite, "f930" },
{ TARGET_CPU_v8, "v8" },
{ TARGET_CPU_supersparc, "supersparc" },
{ TARGET_CPU_v9, "v9" },
{ TARGET_CPU_ultrasparc, "ultrasparc" },
{ 0 }
};
......@@ -167,22 +186,47 @@ sparc_override_options ()
{ "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
/* TEMIC sparclet */
{ "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
/* "v9" is used to specify a true 64 bit architecture.
"v8plus" is what Sun calls Solaris2 running on UltraSPARC's. */
/* "v8plus" is what Sun calls Solaris2.5 running on UltraSPARC's. */
{ "v8plus", PROCESSOR_V8PLUS, MASK_ISA, MASK_V9 },
#if SPARC_ARCH64
{ "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
#endif
/* TI ultrasparc */
{ "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
{ 0 }
};
struct cpu_table *cpu;
struct sparc_cpu_select *sel;
int fpu;
#ifndef SPARC_BI_ARCH
/* Check for unsupported architecture size. */
if (! TARGET_64BIT != DEFAULT_ARCH32_P)
{
error ("%s is not supported by this configuration",
DEFAULT_ARCH32_P ? "-m64" : "-m32");
}
#endif
/* Code model selection. */
sparc_cmodel = SPARC_DEFAULT_CMODEL;
if (sparc_cmodel_string != NULL)
{
if (TARGET_ARCH64)
{
for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
break;
if (cmodel->name == NULL)
error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
else
sparc_cmodel = cmodel->value;
}
else
error ("-mcmodel= is not supported on 32 bit systems");
}
int fpu = TARGET_FPU; /* save current -mfpu status */
fpu = TARGET_FPU; /* save current -mfpu status */
/* Set the default. */
/* Set the default CPU. */
for (def = &cpu_default[0]; def->name; ++def)
if (def->cpu == TARGET_CPU_DEFAULT)
break;
......@@ -284,7 +328,7 @@ static rtx fpconv_stack_temp;
/* Called once for each function. */
void
sparc64_init_expanders ()
sparc_init_expanders ()
{
fpconv_stack_temp = NULL_RTX;
}
......@@ -295,10 +339,10 @@ rtx
sparc64_fpconv_stack_temp ()
{
if (fpconv_stack_temp == NULL_RTX)
fpconv_stack_temp =
assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0);
fpconv_stack_temp =
assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0);
return fpconv_stack_temp;
return fpconv_stack_temp;
}
/* Miscellaneous utilities. */
......@@ -532,7 +576,7 @@ sp64_medium_pic_operand (op, mode)
/* Return 1 if the operand is a data segment reference. This includes
the readonly data segment, or in other words anything but the text segment.
This is needed in the medium/anywhere code model on v9. These values
are accessed with MEDANY_BASE_REG. */
are accessed with EMBMEDANY_BASE_REG. */
int
data_segment_operand (op, mode)
......@@ -4679,8 +4723,8 @@ print_operand (file, x, code)
fputs ("\n\tnop", file);
return;
case '_':
/* Output the Medium/Anywhere code model base register. */
fputs (MEDANY_BASE_REG, file);
/* Output the Embedded Medium/Anywhere code model base register. */
fputs (EMBMEDANY_BASE_REG, file);
return;
case '@':
/* Print out what we are using as the frame pointer. This might
......@@ -4944,7 +4988,7 @@ output_double_int (file, value)
|| GET_CODE (value) == CODE_LABEL
|| GET_CODE (value) == MINUS)))
{
if (!TARGET_V9 || TARGET_MEDLOW)
if (!TARGET_V9 || TARGET_CM_MEDLOW)
{
ASM_OUTPUT_INT (file, const0_rtx);
ASM_OUTPUT_INT (file, value);
......
gcc/config/sparc/sparc.md
......@@ -1777,21 +1777,27 @@
;; Most of the required support for the various code models is here.
;; We can do this because sparcs need the high insn to load the address. We
;; just need to get high to do the right thing for each code model. Then each
;; uses the same "%X+%lo(...)" in the load/store insn.
;; uses the same "%X+%lo(...)" in the load/store insn, though in the case of
;; the medium/middle code model "%lo" is written "%l44".
;; When TARGET_MEDLOW, assume that the upper 32 bits of symbol addresses are
;; When TARGET_CM_MEDLOW, assume that the upper 32 bits of symbol addresses are
;; always 0.
;; When TARGET_MEDANY, the text and data segments have a maximum size of 32
;; bits and may be located anywhere. MEDANY_BASE_REG contains the start
;; When TARGET_CM_MEDMID, the executable must be in the low 16 TB of memory.
;; This corresponds to the low 44 bits, and the %[hml]44 relocs are used.
;; ??? Not implemented yet.
;; When TARGET_CM_EMBMEDANY, the text and data segments have a maximum size of
;; 31 bits and may be located anywhere. EMBMEDANY_BASE_REG contains the start
;; address of the data segment, currently %g4.
;; When TARGET_FULLANY, symbolic addresses are 64 bits.
;; When TARGET_CM_MEDANY, the text and data segments have a maximum size of 31
;; bits and may be located anywhere. The maximum offset from any instruction
;; to the label _GLOBAL_OFFSET_TABLE_ is 31 bits.
(define_insn "*sethi_di_medlow"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand 1 "" "")))
;; The clobber is here because emit_move_sequence assumes the worst case.
(clobber (reg:DI 1))]
"TARGET_MEDLOW && check_pic (1)"
"TARGET_CM_MEDLOW && check_pic (1)"
"sethi %%hi(%a1),%0"
[(set_attr "type" "move")
(set_attr "length" "1")])
......@@ -1799,7 +1805,7 @@
(define_insn "*sethi_di_medium_pic"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand 1 "sp64_medium_pic_operand" "")))]
"(TARGET_MEDLOW || TARGET_MEDANY) && check_pic (1)"
"(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
"sethi %%hi(%a1),%0"
[(set_attr "type" "move")
(set_attr "length" "1")])
......@@ -1807,31 +1813,22 @@
;; WARNING: %0 gets %hi(%1)+%g4.
;; You cannot OR in %lo(%1), it must be added in.
(define_insn "*sethi_di_medany_data"
(define_insn "*sethi_di_embmedany_data"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand 1 "data_segment_operand" "")))
;; The clobber is here because emit_move_sequence assumes the worst case.
(clobber (reg:DI 1))]
"TARGET_MEDANY && check_pic (1)"
"sethi %%hi(%a1),%0; add %0,%%g4,%0"
"TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi %%hi(%a1),%0; add %0,%_,%0"
[(set_attr "type" "move")
(set_attr "length" "2")])
(define_insn "*sethi_di_medany_text"
(define_insn "*sethi_di_embmedany_text"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand 1 "text_segment_operand" "")))
;; The clobber is here because emit_move_sequence assumes the worst case.
(clobber (reg:DI 1))]
"TARGET_MEDANY && check_pic (1)"
"sethi %%uhi(%a1),%%g1; or %%g1,%%ulo(%a1),%%g1; sllx %%g1,32,%%g1; sethi %%hi(%a1),%0; or %0,%%g1,%0"
[(set_attr "type" "move")
(set_attr "length" "5")])
(define_insn "*sethi_di_fullany"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand 1 "" "")))
(clobber (reg:DI 1))]
"TARGET_FULLANY && check_pic (1)"
"TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi %%uhi(%a1),%%g1; or %%g1,%%ulo(%a1),%%g1; sllx %%g1,32,%%g1; sethi %%hi(%a1),%0; or %0,%%g1,%0"
[(set_attr "type" "move")
(set_attr "length" "5")])
......
gcc/config/sparc/splet.h
......@@ -36,12 +36,6 @@ Boston, MA 02111-1307, USA. */
{"broken-saverestore", MASK_BROKEN_SAVERESTORE}, \
{"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE},
#undef CPP_SPEC
#define CPP_SPEC "\
%(cpp_cpu) \
%{mlittle-endian:-D__LITTLE_ENDIAN__} \
"
#undef ASM_SPEC
#define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)"
......
gcc/config/sparc/sysv4.h
......@@ -52,9 +52,7 @@ Boston, MA 02111-1307, USA. */
the Sparc running svr4. __svr4__ is our extension. */
#define CPP_PREDEFINES \
"-Dsparc -Dunix -D__svr4__ \
-Asystem(unix) -Asystem(svr4) -Acpu(sparc) -Amachine(sparc) \
-D__GCC_NEW_VARARGS__"
"-Dsparc -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4)"
/* The native assembler can't compute differences between symbols in different
sections when generating pic code, so we must put jump tables in the
......@@ -201,12 +199,8 @@ do { \
#undef FUNCTION_BLOCK_PROFILER
#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
do { \
if (TARGET_MEDANY) \
fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tor %%0,%%lo(.LLPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne .LLPY%d\n\tadd %%o0,%s,%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \
MEDANY_BASE_REG, (LABELNO), MEDANY_BASE_REG, (LABELNO)); \
else \
fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tld [%%lo(.LLPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(.LLPBX0),%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \
(LABELNO), (LABELNO)); \
fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tld [%%lo(.LLPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(.LLPBX0),%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \
(LABELNO), (LABELNO)); \
} while (0)
/* Output assembler code to FILE to increment the entry-count for
......@@ -216,13 +210,9 @@ do { \
#define BLOCK_PROFILER(FILE, BLOCKNO) \
{ \
int blockn = (BLOCKNO); \
if (TARGET_MEDANY) \
fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tor %%g1,%%lo(.LLPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
else \
fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tld [%%lo(.LLPBX2+%d)+%%g1],%%g2\n\
fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tld [%%lo(.LLPBX2+%d)+%%g1],%%g2\n\
\tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(.LLPBX2+%d)+%%g1]\n", \
4 * blockn, 4 * blockn, 4 * blockn); \
4 * blockn, 4 * blockn, 4 * blockn); \
}
/* A C statement (sans semicolon) to output to the stdio stream
......
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