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riscv-gcc-1
Commit a012718f by Richard Sandiford Committed by Richard Sandiford
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mips-protos.h (gen_int_relational): Delete. 

	* config/mips/mips-protos.h (gen_int_relational): Delete.
	(mips_emit_scc): Declare.
	* config/mips/mips.c (internal_test): Delete.
	(sle_operand, sleu_operand): New functions.
	(map_test_to_internal_test, gen_int_relational): Delete.
	(mips_emit_binary, mips_relational_operand_ok_p)
	(mips_emit_int_relational, mips_zero_if_equal)
	(mips_emit_scc): New functions.
	(gen_conditional_branch): Rework to use mips_emit_int_relational.
	* config/mips/mips.h (PREDICATE_CODES): Add sle_operand and
	sleu_operand.
	* config/mips/mips.md (seq, sne, sgt, sge, slt, sle, sgtu, sgeu)
	(sltu, sleu): Use mips_emit_scc.
	(*sge_[sd]i, *sgeu_[sd]i): New patterns.
	(*sle_[sd]i, *sle_[sd]i_mips16): Use sle_operand.
	(*sleu_[sd]i, *sleu_[sd]i_mips16): Use sleu_operand.

From-SVN: r84808
parent c03eb5a3
Showing with 84 additions and 87 deletions
gcc/ChangeLog
2004-07-16 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (gen_int_relational): Delete.
(mips_emit_scc): Declare.
* config/mips/mips.c (internal_test): Delete.
(sle_operand, sleu_operand): New functions.
(map_test_to_internal_test, gen_int_relational): Delete.
(mips_emit_binary, mips_relational_operand_ok_p)
(mips_emit_int_relational, mips_zero_if_equal)
(mips_emit_scc): New functions.
(gen_conditional_branch): Rework to use mips_emit_int_relational.
* config/mips/mips.h (PREDICATE_CODES): Add sle_operand and
sleu_operand.
* config/mips/mips.md (seq, sne, sgt, sge, slt, sle, sgtu, sgeu)
(sltu, sleu): Use mips_emit_scc.
(*sge_[sd]i, *sgeu_[sd]i): New patterns.
(*sle_[sd]i, *sle_[sd]i_mips16): Use sle_operand.
(*sleu_[sd]i, *sleu_[sd]i_mips16): Use sleu_operand.
2004-07-16 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (*sgt_di_mips16): Fix destination constraint.
2004-07-16 Richard Sandiford <rsandifo@redhat.com>
......
gcc/config/mips/mips-protos.h
......@@ -123,7 +123,7 @@ extern void mips_split_64bit_move (rtx, rtx);
extern const char *mips_output_move (rtx, rtx);
extern rtx mips_gp_save_slot (void);
#ifdef RTX_CODE
extern rtx gen_int_relational (enum rtx_code, rtx, rtx, rtx, int *);
extern bool mips_emit_scc (enum rtx_code, rtx);
extern void gen_conditional_branch (rtx *, enum rtx_code);
#endif
extern void gen_conditional_move (rtx *);
......
gcc/config/mips/mips.h
......@@ -2727,6 +2727,8 @@ typedef struct mips_args {
UNSPEC_VOLATILE }}, \
{"arith_operand", { REG, CONST_INT, CONST, SUBREG }}, \
{"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
{"sle_operand", { CONST_INT }}, \
{"sleu_operand", { CONST_INT }}, \
{"small_int", { CONST_INT }}, \
{"const_float_1_operand", { CONST_DOUBLE }}, \
{"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
......
gcc/config/mips/mips.md
......@@ -6012,14 +6012,7 @@ dsrl\t%3,%3,1\n\
(eq:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_int_relational (EQ, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
{ if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
(define_insn "*seq_si"
[(set (match_operand:SI 0 "register_operand" "=d")
......@@ -6057,20 +6050,15 @@ dsrl\t%3,%3,1\n\
[(set_attr "type" "slt")
(set_attr "mode" "DI")])
;; On the mips16 the default code is better than using sltu.
;; "sne" uses sltu instructions in which the first operand is $0.
;; This isn't possible in mips16 code.
(define_expand "sne"
[(set (match_operand:SI 0 "register_operand")
(ne:SI (match_dup 1)
(match_dup 2)))]
"!TARGET_MIPS16"
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_int_relational (NE, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
{ if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
(define_insn "*sne_si"
[(set (match_operand:SI 0 "register_operand" "=d")
......@@ -6095,13 +6083,7 @@ dsrl\t%3,%3,1\n\
(gt:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_int_relational (GT, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
{ if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
(define_insn "*sgt_si"
[(set (match_operand:SI 0 "register_operand" "=d")
......@@ -6144,26 +6126,32 @@ dsrl\t%3,%3,1\n\
(ge:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
{ if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
gen_int_relational (GE, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
(define_insn "*sge_si"
[(set (match_operand:SI 0 "register_operand" "=d")
(ge:SI (match_operand:SI 1 "register_operand" "d")
(const_int 1)))]
"!TARGET_MIPS16"
"slt\t%0,%.,%1"
[(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn "*sge_di"
[(set (match_operand:DI 0 "register_operand" "=d")
(ge:DI (match_operand:DI 1 "register_operand" "d")
(const_int 1)))]
"TARGET_64BIT && !TARGET_MIPS16"
"slt\t%0,%.,%1"
[(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_expand "slt"
[(set (match_operand:SI 0 "register_operand")
(lt:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_int_relational (LT, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
{ if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
(define_insn "*slt_si"
[(set (match_operand:SI 0 "register_operand" "=d")
......@@ -6216,19 +6204,13 @@ dsrl\t%3,%3,1\n\
(le:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_int_relational (LE, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
{ if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
(define_insn "*sle_si"
[(set (match_operand:SI 0 "register_operand" "=d")
(le:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "I")))]
"!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
(match_operand:SI 2 "sle_operand" "")))]
"!TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt\t%0,%1,%2";
......@@ -6239,8 +6221,8 @@ dsrl\t%3,%3,1\n\
(define_insn "*sle_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t")
(le:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "I")))]
"TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
(match_operand:SI 2 "sle_operand" "")))]
"TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt\t%1,%2";
......@@ -6254,8 +6236,8 @@ dsrl\t%3,%3,1\n\
(define_insn "*sle_di"
[(set (match_operand:DI 0 "register_operand" "=d")
(le:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "small_int" "I")))]
"TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
(match_operand:DI 2 "sle_operand" "")))]
"TARGET_64BIT && !TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt\t%0,%1,%2";
......@@ -6266,8 +6248,8 @@ dsrl\t%3,%3,1\n\
(define_insn "*sle_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=t")
(le:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "small_int" "I")))]
"TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
(match_operand:DI 2 "sle_operand" "")))]
"TARGET_64BIT && TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt\t%1,%2";
......@@ -6283,13 +6265,7 @@ dsrl\t%3,%3,1\n\
(gtu:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_int_relational (GTU, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
{ if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
(define_insn "*sgtu_si"
[(set (match_operand:SI 0 "register_operand" "=d")
......@@ -6332,26 +6308,32 @@ dsrl\t%3,%3,1\n\
(geu:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
{ if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
gen_int_relational (GEU, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
(define_insn "*sge_si"
[(set (match_operand:SI 0 "register_operand" "=d")
(geu:SI (match_operand:SI 1 "register_operand" "d")
(const_int 1)))]
"!TARGET_MIPS16"
"sltu\t%0,%.,%1"
[(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn "*sge_di"
[(set (match_operand:DI 0 "register_operand" "=d")
(geu:DI (match_operand:DI 1 "register_operand" "d")
(const_int 1)))]
"TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%.,%1"
[(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_expand "sltu"
[(set (match_operand:SI 0 "register_operand")
(ltu:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_int_relational (LTU, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
{ if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
(define_insn "*sltu_si"
[(set (match_operand:SI 0 "register_operand" "=d")
......@@ -6404,19 +6386,13 @@ dsrl\t%3,%3,1\n\
(leu:SI (match_dup 1)
(match_dup 2)))]
""
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_int_relational (LEU, operands[0], cmp_operands[0], cmp_operands[1], NULL);
DONE;
})
{ if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
(define_insn "*sleu_si"
[(set (match_operand:SI 0 "register_operand" "=d")
(leu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "I")))]
"!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
(match_operand:SI 2 "sleu_operand" "")))]
"!TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%0,%1,%2";
......@@ -6427,8 +6403,8 @@ dsrl\t%3,%3,1\n\
(define_insn "*sleu_si_mips16"
[(set (match_operand:SI 0 "register_operand" "=t")
(leu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "I")))]
"TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
(match_operand:SI 2 "sleu_operand" "")))]
"TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%1,%2";
......@@ -6442,8 +6418,8 @@ dsrl\t%3,%3,1\n\
(define_insn "*sleu_di"
[(set (match_operand:DI 0 "register_operand" "=d")
(leu:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "small_int" "I")))]
"TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
(match_operand:DI 2 "sleu_operand" "")))]
"TARGET_64BIT && !TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%0,%1,%2";
......@@ -6454,8 +6430,8 @@ dsrl\t%3,%3,1\n\
(define_insn "*sleu_di_mips16"
[(set (match_operand:DI 0 "register_operand" "=t")
(leu:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "small_int" "I")))]
"TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
(match_operand:DI 2 "sleu_operand" "")))]
"TARGET_64BIT && TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%1,%2";
......
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