Skip to content

R
riscv-gcc-1
Commit 9f178d6a by Charles Baylis Committed by Christophe Lyon
Options

re PR target/59142 (internal compiler error while compiling OpenCV 2.4.7) 

2013-12-19  Charles Baylis  <charles.baylis@linaro.org>

	PR target/59142
	gcc/
	* config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb
	patterns.
	* config/arm/ldmstm.md: Regenerate.

From-SVN: r206125
parent 03158648
Showing with 41 additions and 31 deletions
gcc/ChangeLog
2013-12-19 Charles Baylis <charles.baylis@linaro.org>
PR target/59142
* arm/predicates.md (arm_hard_general_register_operand): New
predicate.
* config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb
patterns.
* config/arm/ldmstm.md: Regenerate.
2013-12-19 Charles Baylis <charles.baylis@linaro.org>
PR target/59142
* config/arm/predicates.md (arm_hard_general_register_operand):
New predicate.
(arm_hard_register_operand): Remove.
* config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand
for all patterns.
gcc/config/arm/arm-ldmstm.ml
......@@ -67,10 +67,13 @@ let destreg nregs first op_type thumb =
Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")")
(nregs + 1) (inout_constr op_type) (constr thumb)
let reg_predicate thumb =
if thumb then "low_register_operand" else "arm_hard_general_register_operand"
let write_ldm_set thumb nregs offset opnr first =
let indent = " " in
Printf.printf "%s" (if first then " [" else indent);
Printf.printf "(set (match_operand:SI %d \"arm_hard_general_register_operand\" \"\")\n" opnr;
Printf.printf "(set (match_operand:SI %d \"%s\" \"\")\n" opnr (reg_predicate thumb);
Printf.printf "%s (mem:SI " indent;
begin if offset != 0 then Printf.printf "(plus:SI " end;
Printf.printf "%s" (destreg nregs first IN thumb);
......@@ -84,7 +87,7 @@ let write_stm_set thumb nregs offset opnr first =
begin if offset != 0 then Printf.printf "(plus:SI " end;
Printf.printf "%s" (destreg nregs first IN thumb);
begin if offset != 0 then Printf.printf " (const_int %d))" offset end;
Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_general_register_operand\" \"\"))" indent opnr
Printf.printf ")\n%s (match_operand:SI %d \"%s\" \"\"))" indent opnr (reg_predicate thumb)
let write_ldm_peep_set extra_indent nregs opnr first =
let indent = " " ^ extra_indent in
......
gcc/config/arm/ldmstm.md
......@@ -42,15 +42,15 @@
(define_insn "*thumb_ldm4_ia"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
[(set (match_operand:SI 1 "low_register_operand" "")
(mem:SI (match_operand:SI 5 "s_register_operand" "l")))
(set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 5)
(const_int 4))))
(set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(set (match_operand:SI 3 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 5)
(const_int 8))))
(set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(set (match_operand:SI 4 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 5)
(const_int 12))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
......@@ -82,15 +82,15 @@
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 5 "s_register_operand" "+&l")
(plus:SI (match_dup 5) (const_int 16)))
(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(set (match_operand:SI 1 "low_register_operand" "")
(mem:SI (match_dup 5)))
(set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 5)
(const_int 4))))
(set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(set (match_operand:SI 3 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 5)
(const_int 8))))
(set (match_operand:SI 4 "arm_hard_general_register_operand" "")
(set (match_operand:SI 4 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 5)
(const_int 12))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
......@@ -136,13 +136,13 @@
[(set (match_operand:SI 5 "s_register_operand" "+&l")
(plus:SI (match_dup 5) (const_int 16)))
(set (mem:SI (match_dup 5))
(match_operand:SI 1 "arm_hard_general_register_operand" ""))
(match_operand:SI 1 "low_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 4)))
(match_operand:SI 2 "arm_hard_general_register_operand" ""))
(match_operand:SI 2 "low_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 8)))
(match_operand:SI 3 "arm_hard_general_register_operand" ""))
(match_operand:SI 3 "low_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 5) (const_int 12)))
(match_operand:SI 4 "arm_hard_general_register_operand" ""))])]
(match_operand:SI 4 "low_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5"
"stm%(ia%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store4")])
......@@ -490,12 +490,12 @@
(define_insn "*thumb_ldm3_ia"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
[(set (match_operand:SI 1 "low_register_operand" "")
(mem:SI (match_operand:SI 4 "s_register_operand" "l")))
(set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 4)
(const_int 4))))
(set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(set (match_operand:SI 3 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 4)
(const_int 8))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
......@@ -524,12 +524,12 @@
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 4 "s_register_operand" "+&l")
(plus:SI (match_dup 4) (const_int 12)))
(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(set (match_operand:SI 1 "low_register_operand" "")
(mem:SI (match_dup 4)))
(set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 4)
(const_int 4))))
(set (match_operand:SI 3 "arm_hard_general_register_operand" "")
(set (match_operand:SI 3 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 4)
(const_int 8))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
......@@ -571,11 +571,11 @@
[(set (match_operand:SI 4 "s_register_operand" "+&l")
(plus:SI (match_dup 4) (const_int 12)))
(set (mem:SI (match_dup 4))
(match_operand:SI 1 "arm_hard_general_register_operand" ""))
(match_operand:SI 1 "low_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 4)))
(match_operand:SI 2 "arm_hard_general_register_operand" ""))
(match_operand:SI 2 "low_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 4) (const_int 8)))
(match_operand:SI 3 "arm_hard_general_register_operand" ""))])]
(match_operand:SI 3 "low_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4"
"stm%(ia%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "store3")])
......@@ -876,9 +876,9 @@
(define_insn "*thumb_ldm2_ia"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
[(set (match_operand:SI 1 "low_register_operand" "")
(mem:SI (match_operand:SI 3 "s_register_operand" "l")))
(set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 3)
(const_int 4))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2"
......@@ -904,9 +904,9 @@
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 3 "s_register_operand" "+&l")
(plus:SI (match_dup 3) (const_int 8)))
(set (match_operand:SI 1 "arm_hard_general_register_operand" "")
(set (match_operand:SI 1 "low_register_operand" "")
(mem:SI (match_dup 3)))
(set (match_operand:SI 2 "arm_hard_general_register_operand" "")
(set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 3)
(const_int 4))))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
......@@ -944,9 +944,9 @@
[(set (match_operand:SI 3 "s_register_operand" "+&l")
(plus:SI (match_dup 3) (const_int 8)))
(set (mem:SI (match_dup 3))
(match_operand:SI 1 "arm_hard_general_register_operand" ""))
(match_operand:SI 1 "low_register_operand" ""))
(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
(match_operand:SI 2 "arm_hard_general_register_operand" ""))])]
(match_operand:SI 2 "low_register_operand" ""))])]
"TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3"
"stm%(ia%)\t%3!, {%1, %2}"
[(set_attr "type" "store2")])
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment