Skip to content

R
riscv-gcc-1
Commit 9e2befc2 by Jim Wilson
Options

(PREDICATE_CODES): Add cint8_operand. 

From-SVN: r7643
parent a62eb16f
Showing with 1 additions and 0 deletions
gcc/config/alpha/alpha.h
......@@ -1811,6 +1811,7 @@ literal_section () \
{"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
{"cint8_operand", {CONST_INT}}, \
{"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
{"add_operand", {SUBREG, REG, CONST_INT}}, \
{"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment