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Commit 9e200aaf by Kelley Cook Committed by H.J. Lu
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i386.c: Rename pni to sse3. 

2004-02-23  Kelley Cook  <kcook@gcc.gnu.org>

	* config/i386/i386.c: Rename pni to sse3.
	* config/i386/i386.h: Likewise.
        * config/i386/i386.md: Likewise.
	* config/i386/pmmintrin.h: Likewise.
	* doc/extend.texi: Likewise.
	* doc/invoke.texi: Likewise.

From-SVN: r78349
parent 4a368ffd
Showing with 60 additions and 51 deletions
gcc/ChangeLog
2004-02-23 Kelley Cook <kcook@gcc.gnu.org>
* config/i386/i386.c: Rename pni to sse3.
* config/i386/i386.h: Likewise.
* config/i386/i386.md: Likewise.
* config/i386/pmmintrin.h: Likewise.
* doc/extend.texi: Likewise.
* doc/invoke.texi: Likewise.
2004-02-23 Zack Weinberg <zack@codesourcery.com> 2004-02-23 Zack Weinberg <zack@codesourcery.com>
Kazu Hirata <kazu@cs.umass.edu> Kazu Hirata <kazu@cs.umass.edu>
......
gcc/config/i386/i386.c
...@@ -1391,8 +1391,8 @@ override_options (void) ...@@ -1391,8 +1391,8 @@ override_options (void)
if (x86_arch_always_fancy_math_387 & (1 << ix86_arch)) if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
target_flags &= ~MASK_NO_FANCY_MATH_387; target_flags &= ~MASK_NO_FANCY_MATH_387;
/* Turn on SSE2 builtins for -mpni. */ /* Turn on SSE2 builtins for -msse3. */
if (TARGET_PNI) if (TARGET_SSE3)
target_flags |= MASK_SSE2; target_flags |= MASK_SSE2;
/* Turn on SSE builtins for -msse2. */ /* Turn on SSE builtins for -msse2. */
...@@ -13072,13 +13072,13 @@ static const struct builtin_description bdesc_2arg[] = ...@@ -13072,13 +13072,13 @@ static const struct builtin_description bdesc_2arg[] =
{ MASK_SSE2, CODE_FOR_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 }, { MASK_SSE2, CODE_FOR_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
{ MASK_SSE2, CODE_FOR_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 }, { MASK_SSE2, CODE_FOR_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
/* PNI MMX */ /* SSE3 MMX */
{ MASK_PNI, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 }, { MASK_SSE3, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
{ MASK_PNI, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 }, { MASK_SSE3, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
{ MASK_PNI, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 }, { MASK_SSE3, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
{ MASK_PNI, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 }, { MASK_SSE3, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
{ MASK_PNI, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 }, { MASK_SSE3, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
{ MASK_PNI, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 } { MASK_SSE3, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
}; };
static const struct builtin_description bdesc_1arg[] = static const struct builtin_description bdesc_1arg[] =
...@@ -13126,10 +13126,10 @@ static const struct builtin_description bdesc_1arg[] = ...@@ -13126,10 +13126,10 @@ static const struct builtin_description bdesc_1arg[] =
{ MASK_SSE2, CODE_FOR_sse2_movq, 0, IX86_BUILTIN_MOVQ, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_movq, 0, IX86_BUILTIN_MOVQ, 0, 0 },
/* PNI */ /* SSE3 */
{ MASK_PNI, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 }, { MASK_SSE3, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
{ MASK_PNI, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 }, { MASK_SSE3, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
{ MASK_PNI, CODE_FOR_movddup, 0, IX86_BUILTIN_MOVDDUP, 0, 0 } { MASK_SSE3, CODE_FOR_movddup, 0, IX86_BUILTIN_MOVDDUP, 0, 0 }
}; };
void void
...@@ -13755,23 +13755,23 @@ ix86_init_mmx_sse_builtins (void) ...@@ -13755,23 +13755,23 @@ ix86_init_mmx_sse_builtins (void)
def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128); def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
/* Prescott New Instructions. */ /* Prescott New Instructions. */
def_builtin (MASK_PNI, "__builtin_ia32_monitor", def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
void_ftype_pcvoid_unsigned_unsigned, void_ftype_pcvoid_unsigned_unsigned,
IX86_BUILTIN_MONITOR); IX86_BUILTIN_MONITOR);
def_builtin (MASK_PNI, "__builtin_ia32_mwait", def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
void_ftype_unsigned_unsigned, void_ftype_unsigned_unsigned,
IX86_BUILTIN_MWAIT); IX86_BUILTIN_MWAIT);
def_builtin (MASK_PNI, "__builtin_ia32_movshdup", def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
v4sf_ftype_v4sf, v4sf_ftype_v4sf,
IX86_BUILTIN_MOVSHDUP); IX86_BUILTIN_MOVSHDUP);
def_builtin (MASK_PNI, "__builtin_ia32_movsldup", def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
v4sf_ftype_v4sf, v4sf_ftype_v4sf,
IX86_BUILTIN_MOVSLDUP); IX86_BUILTIN_MOVSLDUP);
def_builtin (MASK_PNI, "__builtin_ia32_lddqu", def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU); v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
def_builtin (MASK_PNI, "__builtin_ia32_loadddup", def_builtin (MASK_SSE3, "__builtin_ia32_loadddup",
v2df_ftype_pcdouble, IX86_BUILTIN_LOADDDUP); v2df_ftype_pcdouble, IX86_BUILTIN_LOADDDUP);
def_builtin (MASK_PNI, "__builtin_ia32_movddup", def_builtin (MASK_SSE3, "__builtin_ia32_movddup",
v2df_ftype_v2df, IX86_BUILTIN_MOVDDUP); v2df_ftype_v2df, IX86_BUILTIN_MOVDDUP);
} }
......
gcc/config/i386/i386.h
...@@ -121,7 +121,7 @@ extern int target_flags; ...@@ -121,7 +121,7 @@ extern int target_flags;
#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
#define MASK_PNI 0x00010000 /* Support PNI regs/builtins */ #define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */
#define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */ #define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */
#define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */ #define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */
#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */ #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
...@@ -304,7 +304,7 @@ extern int x86_prefetch_sse; ...@@ -304,7 +304,7 @@ extern int x86_prefetch_sse;
#define TARGET_SSE ((target_flags & MASK_SSE) != 0) #define TARGET_SSE ((target_flags & MASK_SSE) != 0)
#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
#define TARGET_PNI ((target_flags & MASK_PNI) != 0) #define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0)
#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
&& (ix86_fpmath & FPMATH_387)) && (ix86_fpmath & FPMATH_387))
...@@ -400,10 +400,10 @@ extern int x86_prefetch_sse; ...@@ -400,10 +400,10 @@ extern int x86_prefetch_sse;
N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
{ "no-sse2", -MASK_SSE2, \ { "no-sse2", -MASK_SSE2, \
N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
{ "pni", MASK_PNI, \ { "sse3", MASK_SSE3, \
N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\ N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
{ "no-pni", -MASK_PNI, \ { "no-sse3", -MASK_SSE3, \
N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\ N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
{ "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
N_("sizeof(long double) is 16") }, \ N_("sizeof(long double) is 16") }, \
{ "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
...@@ -617,8 +617,8 @@ extern int x86_prefetch_sse; ...@@ -617,8 +617,8 @@ extern int x86_prefetch_sse;
builtin_define ("__SSE__"); \ builtin_define ("__SSE__"); \
if (TARGET_SSE2) \ if (TARGET_SSE2) \
builtin_define ("__SSE2__"); \ builtin_define ("__SSE2__"); \
if (TARGET_PNI) \ if (TARGET_SSE3) \
builtin_define ("__PNI__"); \ builtin_define ("__SSE3__"); \
if (TARGET_SSE_MATH && TARGET_SSE) \ if (TARGET_SSE_MATH && TARGET_SSE) \
builtin_define ("__SSE_MATH__"); \ builtin_define ("__SSE_MATH__"); \
if (TARGET_SSE_MATH && TARGET_SSE2) \ if (TARGET_SSE_MATH && TARGET_SSE2) \
......
gcc/config/i386/i386.md
...@@ -22930,13 +22930,13 @@ ...@@ -22930,13 +22930,13 @@
[(set_attr "type" "sse") [(set_attr "type" "sse")
(set_attr "memory" "unknown")]) (set_attr "memory" "unknown")])
;; PNI ;; SSE3
(define_insn "mwait" (define_insn "mwait"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "a") [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
(match_operand:SI 1 "register_operand" "c")] (match_operand:SI 1 "register_operand" "c")]
UNSPECV_MWAIT)] UNSPECV_MWAIT)]
"TARGET_PNI" "TARGET_SSE3"
"mwait\t%0, %1" "mwait\t%0, %1"
[(set_attr "length" "3")]) [(set_attr "length" "3")])
...@@ -22945,18 +22945,18 @@ ...@@ -22945,18 +22945,18 @@
(match_operand:SI 1 "register_operand" "c") (match_operand:SI 1 "register_operand" "c")
(match_operand:SI 2 "register_operand" "d")] (match_operand:SI 2 "register_operand" "d")]
UNSPECV_MONITOR)] UNSPECV_MONITOR)]
"TARGET_PNI" "TARGET_SSE3"
"monitor\t%0, %1, %2" "monitor\t%0, %1, %2"
[(set_attr "length" "3")]) [(set_attr "length" "3")])
;; PNI arithmetic ;; SSE3 arithmetic
(define_insn "addsubv4sf3" (define_insn "addsubv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")] (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
UNSPEC_ADDSUB))] UNSPEC_ADDSUB))]
"TARGET_PNI" "TARGET_SSE3"
"addsubps\t{%2, %0|%0, %2}" "addsubps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
...@@ -22966,7 +22966,7 @@ ...@@ -22966,7 +22966,7 @@
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
(match_operand:V2DF 2 "nonimmediate_operand" "xm")] (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
UNSPEC_ADDSUB))] UNSPEC_ADDSUB))]
"TARGET_PNI" "TARGET_SSE3"
"addsubpd\t{%2, %0|%0, %2}" "addsubpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "V2DF")]) (set_attr "mode" "V2DF")])
...@@ -22976,7 +22976,7 @@ ...@@ -22976,7 +22976,7 @@
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")] (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
UNSPEC_HADD))] UNSPEC_HADD))]
"TARGET_PNI" "TARGET_SSE3"
"haddps\t{%2, %0|%0, %2}" "haddps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
...@@ -22986,7 +22986,7 @@ ...@@ -22986,7 +22986,7 @@
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
(match_operand:V2DF 2 "nonimmediate_operand" "xm")] (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
UNSPEC_HADD))] UNSPEC_HADD))]
"TARGET_PNI" "TARGET_SSE3"
"haddpd\t{%2, %0|%0, %2}" "haddpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "V2DF")]) (set_attr "mode" "V2DF")])
...@@ -22996,7 +22996,7 @@ ...@@ -22996,7 +22996,7 @@
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V4SF 2 "nonimmediate_operand" "xm")] (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
UNSPEC_HSUB))] UNSPEC_HSUB))]
"TARGET_PNI" "TARGET_SSE3"
"hsubps\t{%2, %0|%0, %2}" "hsubps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
...@@ -23006,7 +23006,7 @@ ...@@ -23006,7 +23006,7 @@
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
(match_operand:V2DF 2 "nonimmediate_operand" "xm")] (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
UNSPEC_HSUB))] UNSPEC_HSUB))]
"TARGET_PNI" "TARGET_SSE3"
"hsubpd\t{%2, %0|%0, %2}" "hsubpd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd") [(set_attr "type" "sseadd")
(set_attr "mode" "V2DF")]) (set_attr "mode" "V2DF")])
...@@ -23015,7 +23015,7 @@ ...@@ -23015,7 +23015,7 @@
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF (unspec:V4SF
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))] [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
"TARGET_PNI" "TARGET_SSE3"
"movshdup\t{%1, %0|%0, %1}" "movshdup\t{%1, %0|%0, %1}"
[(set_attr "type" "sse") [(set_attr "type" "sse")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
...@@ -23024,7 +23024,7 @@ ...@@ -23024,7 +23024,7 @@
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x")
(unspec:V4SF (unspec:V4SF
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))] [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
"TARGET_PNI" "TARGET_SSE3"
"movsldup\t{%1, %0|%0, %1}" "movsldup\t{%1, %0|%0, %1}"
[(set_attr "type" "sse") [(set_attr "type" "sse")
(set_attr "mode" "V4SF")]) (set_attr "mode" "V4SF")])
...@@ -23033,7 +23033,7 @@ ...@@ -23033,7 +23033,7 @@
[(set (match_operand:V16QI 0 "register_operand" "=x") [(set (match_operand:V16QI 0 "register_operand" "=x")
(unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")] (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
UNSPEC_LDQQU))] UNSPEC_LDQQU))]
"TARGET_PNI" "TARGET_SSE3"
"lddqu\t{%1, %0|%0, %1}" "lddqu\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
...@@ -23041,7 +23041,7 @@ ...@@ -23041,7 +23041,7 @@
(define_insn "loadddup" (define_insn "loadddup"
[(set (match_operand:V2DF 0 "register_operand" "=x") [(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))] (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
"TARGET_PNI" "TARGET_SSE3"
"movddup\t{%1, %0|%0, %1}" "movddup\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
...@@ -23051,7 +23051,7 @@ ...@@ -23051,7 +23051,7 @@
(vec_duplicate:V2DF (vec_duplicate:V2DF
(vec_select:DF (match_operand:V2DF 1 "register_operand" "x") (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
(parallel [(const_int 0)]))))] (parallel [(const_int 0)]))))]
"TARGET_PNI" "TARGET_SSE3"
"movddup\t{%1, %0|%0, %1}" "movddup\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
gcc/config/i386/pmmintrin.h
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#ifndef _PMMINTRIN_H_INCLUDED #ifndef _PMMINTRIN_H_INCLUDED
#define _PMMINTRIN_H_INCLUDED #define _PMMINTRIN_H_INCLUDED
#ifdef __PNI__ #ifdef __SSE3__
#include <xmmintrin.h> #include <xmmintrin.h>
#include <emmintrin.h> #include <emmintrin.h>
...@@ -127,6 +127,6 @@ _mm_mwait (unsigned int __E, unsigned int __H) ...@@ -127,6 +127,6 @@ _mm_mwait (unsigned int __E, unsigned int __H)
#define _mm_mwait(E, H) __builtin_ia32_mwait ((E), (H)) #define _mm_mwait(E, H) __builtin_ia32_mwait ((E), (H))
#endif #endif
#endif /* __PNI__ */ #endif /* __SSE3__ */
#endif /* _PMMINTRIN_H_INCLUDED */ #endif /* _PMMINTRIN_H_INCLUDED */
gcc/doc/extend.texi
...@@ -5977,7 +5977,7 @@ Generates the @code{movhps} machine instruction as a store to memory. ...@@ -5977,7 +5977,7 @@ Generates the @code{movhps} machine instruction as a store to memory.
Generates the @code{movlps} machine instruction as a store to memory. Generates the @code{movlps} machine instruction as a store to memory.
@end table @end table
The following built-in functions are available when @option{-mpni} is used. The following built-in functions are available when @option{-msse3} is used.
All of them generate the machine instruction that is part of the name. All of them generate the machine instruction that is part of the name.
@smallexample @smallexample
...@@ -5995,7 +5995,7 @@ v4sf __builtin_ia32_movsldup (v4sf) ...@@ -5995,7 +5995,7 @@ v4sf __builtin_ia32_movsldup (v4sf)
void __builtin_ia32_mwait (unsigned int, unsigned int) void __builtin_ia32_mwait (unsigned int, unsigned int)
@end smallexample @end smallexample
The following built-in functions are available when @option{-mpni} is used. The following built-in functions are available when @option{-msse3} is used.
@table @code @table @code
@item v2df __builtin_ia32_loadddup (double const *) @item v2df __builtin_ia32_loadddup (double const *)
......
gcc/doc/invoke.texi
...@@ -488,7 +488,7 @@ in the following sections. ...@@ -488,7 +488,7 @@ in the following sections.
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol -mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
-mno-wide-multiply -mrtd -malign-double @gol -mno-wide-multiply -mrtd -malign-double @gol
-mpreferred-stack-boundary=@var{num} @gol -mpreferred-stack-boundary=@var{num} @gol
-mmmx -msse -msse2 -mpni -m3dnow @gol -mmmx -msse -msse2 -msse3 -m3dnow @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol -mthreads -mno-align-stringops -minline-all-stringops @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol -mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol -m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
...@@ -8385,8 +8385,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. ...@@ -8385,8 +8385,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@itemx -mno-sse @itemx -mno-sse
@item -msse2 @item -msse2
@itemx -mno-sse2 @itemx -mno-sse2
@item -mpni @item -msse3
@itemx -mno-pni @itemx -mno-sse3
@item -m3dnow @item -m3dnow
@itemx -mno-3dnow @itemx -mno-3dnow
@opindex mmmx @opindex mmmx
...@@ -8396,7 +8396,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. ...@@ -8396,7 +8396,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@opindex m3dnow @opindex m3dnow
@opindex mno-3dnow @opindex mno-3dnow
These switches enable or disable the use of built-in functions that allow These switches enable or disable the use of built-in functions that allow
direct access to the MMX, SSE, SSE2, PNI and 3Dnow extensions of the direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
instruction set. instruction set.
@xref{X86 Built-in Functions}, for details of the functions enabled @xref{X86 Built-in Functions}, for details of the functions enabled
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