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Commit 9d901b0e by Jakub Jelinek Committed by Jakub Jelinek
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sse.md (avx2_gathersi<mode>, [...]): Add clobber of match_scratch... 

	* config/i386/sse.md (avx2_gathersi<mode>,
	avx2_gatherdi<mode>, avx2_gatherdi<mode>256): Add clobber of
	match_scratch, change memory_operand to register_operand,
	add (mem:BLK (scratch)) use.
	(*avx2_gathersi<mode>, *avx2_gatherdi<mode>,
	*avx2_gatherdi<mode>256): Add clobber of match_scratch,
	add earlyclobber to the output operand and match_scratch,
	add (mem:BLK (scratch)) use, change the other mem to match_operand.
	Use %p6 instead of %c6 in the pattern.
	* config/i386/i386.c (ix86_expand_builtin): Adjust for
	operand 2 being a Pmode register_operand instead of memory_operand.

From-SVN: r179869
parent 15bf7d19
Showing with 75 additions and 54 deletions
gcc/ChangeLog
2011-10-12 Jakub Jelinek <jakub@redhat.com>
* config/i386/sse.md (avx2_gathersi<mode>,
avx2_gatherdi<mode>, avx2_gatherdi<mode>256): Add clobber of
match_scratch, change memory_operand to register_operand,
add (mem:BLK (scratch)) use.
(*avx2_gathersi<mode>, *avx2_gatherdi<mode>,
*avx2_gatherdi<mode>256): Add clobber of match_scratch,
add earlyclobber to the output operand and match_scratch,
add (mem:BLK (scratch)) use, change the other mem to match_operand.
Use %p6 instead of %c6 in the pattern.
* config/i386/i386.c (ix86_expand_builtin): Adjust for
operand 2 being a Pmode register_operand instead of memory_operand.
2011-10-12 Kai Tietz <ktietz@redhat.com>
* config/i386/i386.md (simple_return): Disable
gcc/config/i386/i386.c
......@@ -28748,7 +28748,6 @@ rdrand_step:
op4 = expand_normal (arg4);
/* Note the arg order is different from the operand order. */
mode0 = insn_data[icode].operand[1].mode;
mode1 = insn_data[icode].operand[2].mode;
mode2 = insn_data[icode].operand[3].mode;
mode3 = insn_data[icode].operand[4].mode;
mode4 = insn_data[icode].operand[5].mode;
......@@ -28762,12 +28761,11 @@ rdrand_step:
if (GET_MODE (op1) != Pmode)
op1 = convert_to_mode (Pmode, op1, 1);
op1 = force_reg (Pmode, op1);
op1 = gen_rtx_MEM (mode1, op1);
if (!insn_data[icode].operand[1].predicate (op0, mode0))
op0 = copy_to_mode_reg (mode0, op0);
if (!insn_data[icode].operand[2].predicate (op1, mode1))
op1 = copy_to_mode_reg (mode1, op1);
if (!insn_data[icode].operand[2].predicate (op1, Pmode))
op1 = copy_to_mode_reg (Pmode, op1);
if (!insn_data[icode].operand[3].predicate (op2, mode2))
op2 = copy_to_mode_reg (mode2, op2);
if (!insn_data[icode].operand[4].predicate (op3, mode3))
gcc/config/i386/sse.md
......@@ -12524,55 +12524,61 @@
(V8SI "V8SI") (V8SF "V8SI")])
(define_expand "avx2_gathersi<mode>"
[(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
(unspec:VEC_GATHER_MODE
[(match_operand:VEC_GATHER_MODE 1 "register_operand" "")
(match_operand:<ssescalarmode> 2 "memory_operand" "")
(match_operand:<VEC_GATHER_MODE> 3 "register_operand" "")
(match_operand:VEC_GATHER_MODE 4 "register_operand" "")
(match_operand:SI 5 "const1248_operand " "")]
UNSPEC_GATHER))]
[(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
(unspec:VEC_GATHER_MODE
[(match_operand:VEC_GATHER_MODE 1 "register_operand" "")
(match_operand 2 "register_operand" "")
(mem:BLK (scratch))
(match_operand:<VEC_GATHER_MODE> 3 "register_operand" "")
(match_operand:VEC_GATHER_MODE 4 "register_operand" "")
(match_operand:SI 5 "const1248_operand " "")]
UNSPEC_GATHER))
(clobber (match_scratch:VEC_GATHER_MODE 6 ""))])]
"TARGET_AVX2")
(define_insn "*avx2_gathersi<mode>"
[(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=x")
[(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x")
(unspec:VEC_GATHER_MODE
[(match_operand:VEC_GATHER_MODE 1 "register_operand" "0")
(mem:<ssescalarmode>
(match_operand:P 2 "register_operand" "r"))
(match_operand:<VEC_GATHER_MODE> 3 "register_operand" "x")
(match_operand:VEC_GATHER_MODE 4 "register_operand" "x")
(match_operand:SI 5 "const1248_operand" "n")]
UNSPEC_GATHER))]
[(match_operand:VEC_GATHER_MODE 2 "register_operand" "0")
(match_operand:P 3 "register_operand" "r")
(mem:BLK (scratch))
(match_operand:<VEC_GATHER_MODE> 4 "register_operand" "x")
(match_operand:VEC_GATHER_MODE 5 "register_operand" "1")
(match_operand:SI 6 "const1248_operand" "n")]
UNSPEC_GATHER))
(clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))]
"TARGET_AVX2"
"v<gthrfirstp>gatherd<gthrlastp>\t{%4, (%2, %3, %c5), %0|%0, (%2, %3, %c5), %4}"
"v<gthrfirstp>gatherd<gthrlastp>\t{%1, (%3, %4, %p6), %0|%0, (%3, %4, %p6), %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "vex")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "avx2_gatherdi<mode>"
[(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
(unspec:VEC_GATHER_MODE
[(match_operand:VEC_GATHER_MODE 1 "register_operand" "")
(match_operand:<ssescalarmode> 2 "memory_operand" "")
(match_operand:<AVXMODE48P_DI> 3 "register_operand" "")
(match_operand:VEC_GATHER_MODE 4 "register_operand" "")
(match_operand:SI 5 "const1248_operand " "")]
UNSPEC_GATHER))]
[(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
(unspec:VEC_GATHER_MODE
[(match_operand:VEC_GATHER_MODE 1 "register_operand" "")
(match_operand 2 "register_operand" "")
(mem:BLK (scratch))
(match_operand:<AVXMODE48P_DI> 3 "register_operand" "")
(match_operand:VEC_GATHER_MODE 4 "register_operand" "")
(match_operand:SI 5 "const1248_operand " "")]
UNSPEC_GATHER))
(clobber (match_scratch:VEC_GATHER_MODE 6 ""))])]
"TARGET_AVX2")
(define_insn "*avx2_gatherdi<mode>"
[(set (match_operand:AVXMODE48P_DI 0 "register_operand" "=x")
[(set (match_operand:AVXMODE48P_DI 0 "register_operand" "=&x")
(unspec:AVXMODE48P_DI
[(match_operand:AVXMODE48P_DI 1 "register_operand" "0")
(mem:<ssescalarmode>
(match_operand:P 2 "register_operand" "r"))
(match_operand:<AVXMODE48P_DI> 3 "register_operand" "x")
(match_operand:AVXMODE48P_DI 4 "register_operand" "x")
(match_operand:SI 5 "const1248_operand" "n")]
UNSPEC_GATHER))]
[(match_operand:AVXMODE48P_DI 2 "register_operand" "0")
(match_operand:P 3 "register_operand" "r")
(mem:BLK (scratch))
(match_operand:<AVXMODE48P_DI> 4 "register_operand" "x")
(match_operand:AVXMODE48P_DI 5 "register_operand" "1")
(match_operand:SI 6 "const1248_operand" "n")]
UNSPEC_GATHER))
(clobber (match_scratch:AVXMODE48P_DI 1 "=&x"))]
"TARGET_AVX2"
"v<gthrfirstp>gatherq<gthrlastp>\t{%4, (%2, %3, %c5), %0|%0, (%2, %3, %c5), %4}"
"v<gthrfirstp>gatherq<gthrlastp>\t{%1, (%3, %4, %p6), %0|%0, (%3, %4, %p6), %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "vex")
(set_attr "mode" "<sseinsnmode>")])
......@@ -12580,28 +12586,31 @@
;; Special handling for VEX.256 with float arguments
;; since there're still xmms as operands
(define_expand "avx2_gatherdi<mode>256"
[(set (match_operand:VI4F_128 0 "register_operand" "")
(unspec:VI4F_128
[(match_operand:VI4F_128 1 "register_operand" "")
(match_operand:<ssescalarmode> 2 "memory_operand" "")
(match_operand:V4DI 3 "register_operand" "")
(match_operand:VI4F_128 4 "register_operand" "")
(match_operand:SI 5 "const1248_operand " "")]
UNSPEC_GATHER))]
[(parallel [(set (match_operand:VI4F_128 0 "register_operand" "")
(unspec:VI4F_128
[(match_operand:VI4F_128 1 "register_operand" "")
(match_operand 2 "register_operand" "")
(mem:BLK (scratch))
(match_operand:V4DI 3 "register_operand" "")
(match_operand:VI4F_128 4 "register_operand" "")
(match_operand:SI 5 "const1248_operand " "")]
UNSPEC_GATHER))
(clobber (match_scratch:VI4F_128 6 ""))])]
"TARGET_AVX2")
(define_insn "*avx2_gatherdi<mode>256"
[(set (match_operand:VI4F_128 0 "register_operand" "=x")
(unspec:VI4F_128
[(match_operand:VI4F_128 1 "register_operand" "0")
(mem:<ssescalarmode>
(match_operand:P 2 "register_operand" "r"))
(match_operand:V4DI 3 "register_operand" "x")
(match_operand:VI4F_128 4 "register_operand" "x")
(match_operand:SI 5 "const1248_operand" "n")]
UNSPEC_GATHER))]
[(match_operand:VI4F_128 2 "register_operand" "0")
(match_operand:P 3 "register_operand" "r")
(mem:BLK (scratch))
(match_operand:V4DI 4 "register_operand" "x")
(match_operand:VI4F_128 5 "register_operand" "1")
(match_operand:SI 6 "const1248_operand" "n")]
UNSPEC_GATHER))
(clobber (match_scratch:VI4F_128 1 "=&x"))]
"TARGET_AVX2"
"v<gthrfirstp>gatherq<gthrlastp>\t{%4, (%2, %3, %c5), %0|%0, (%2, %3, %c5), %4}"
"v<gthrfirstp>gatherq<gthrlastp>\t{%1, (%3, %4, %p6), %0|%0, (%3, %4, %p6), %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "vex")
(set_attr "mode" "<sseinsnmode>")])
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